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    Imec

    院校EST. 1984
    935论文总数
    1.5万引用总数

    Interuniversity Microelectronics Centre (IMEC) is an international research & development organization, active in the fields of nanoelectronics and digital technologies, with headquarters in Belgium. Luc Van den hove has served as President and CEO since 2009.In September 2016, imec merged with the Flemish digital research center, iMinds.

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    论文(935)

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    1Unlocking the Full Potential of SSRM for GaAs: Nanoscale Carrier Profiling in Nano-Ridge Laser Diodes
    L. Wouters, P. Lagrain, N. Peric, P.Y. Hsieh, P. Swekis, A.M.R. Sharma, Y. Mols, I. De Wolf, B. Kunert, T. Hantschel

    Owing to its direct bandgap and high electron mobility, gallium arsenide (GaAs) plays a key role in the development of high-performance electronic and optoelectronic devices. Accordingly, the accurate characterization of two-dimensional carrier distributions is essential to support their integration. Scanning spreading resistance microscopy (SSRM) is a well-established method for quantitative carrier profiling in silicon, while its application to III-V semiconductors is complicated by the non-ohmic nature of the tip-sample contact. Therefore, we present a systematic study of SSRM on GaAs, focusing on the optimization of both electrical (bias) and mechanical (force and repeated scanning) measurement conditions. Key performance metrics, including dynamic range, doping sensitivity, and repeatability, are evaluated to assess measurement reliability. Building on these insights, we demonstrate the applicability of SSRM to advanced nanoscale devices through a case study supporting the growth optimization of monolithically integrated GaAs nano-ridge laser diodes on silicon. The complex geometry and facet-dependent growth in these structures lead to non-trivial active dopant distributions, making them an ideal platform to highlight the capabilities of SSRM. Finally, we extend the use of SSRM to failure analysis by leveraging the reverse tip sample (RTS) methodology for site-specific electrical characterization of electrical stress-induced localized degradation defects in aged GaAs-on-Si laser diodes. In summary, this work establishes SSRM as a powerful technique for quantitative two-dimensional carrier profiling in both n- and p-type GaAs and demonstrates its value for the development, optimization, and failure analysis of advanced GaAs-based devices.

    2027Materials Science in Semiconductor Processing(2027)
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    2Overview of Defect Characterization on GaN Stacks for Vertical Device Fabrication on 200 Mm Engineered QST® Substrates
    Sourish Banerjee, Han, Giulia Napolitano,Albert Minj,Olivier Richard,Erik Rosseel,Karen Geens,Md Arif Khan, Sebastian Beer, Vlad Odnoblyudov,Benoit Bakeroot,Stefaan Decoutere,

    The increasing demand for high-voltage (>1200 V) power devices has driven the epitaxy of thick GaN buffers on top of mechanically robust substrates, such as engineered QST (R) substrates. This study investigates the material crystalline defects in vertical GaN buffers grown via metalorganic chemical vapor deposition on 200 mm QST (R), with and without pre-grown epitaxial lateral overgrown (ELOG) buffers. We present a systematic analysis of the threading dislocation density (TDD) using several destructive and non-destructive techniques such as transmission electron microscopy (TEM), cathodoluminescence (CL), electron channeling contrast imaging (ECCI), x-ray diffraction (XRD) and scanning probe microscopy (SPM). They reveal different dislocation types, i.e. edge, mixed and screw TDs. TEM reveals a similar to 5 times TDD reduction for stacks employing ELOG buffers. ECCI, CL and XRD complement one another with similar to 2-2.5 times reduced TDD on ELOG buffer. Whereas CL reveals all TDs involved in non-radiative recombination, ambiguity remains in ascribing the specific TD type. ECCI primarily identifies mixed TDs. XRD analyses of GaN(0002) and (10-12) reflections reveal a systematic improvement of crystal quality with increasing drift layer (DL) thickness. ELOG buffer reveals similar to 4 times stronger screw TD reduction and >6 times stronger edge TD reduction with increasing DL thickness, compared to the one without. Conductive atomic force microscopy measurements show that only similar to 0.1%-0.2% of the total TDs are electrically active contributing to vertical leakage, with >3 times reduction of such TDs in the ELOG buffer. Cross-sectional SPM, CL and ECCI imaging further validate the reduced defectivity in ELOG-enabled stacks. The scanning capacitance microscope (SCM) |dC/dV| maps show reduced amplitude at defect sites and CL imaging clearly visualizes these darker non-radiative recombination regions, whereas ECCI complements these observations. In summary, this study presents a comprehensive defectivity analysis of GaN-on-QST (R) substrates with ELOG buffers, demonstrating their potential for vertical GaN device fabrication and up-scaling.

    2026JOURNAL OF PHYSICS D-APPLIED PHYSICS(2026)引用:42
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    3Power Spectral Density Analysis of Solid-State Nanopore Signals: Application to Stability Estimation
    Pratima Upretee, Eric Beamish, Wouter Botermans, Matteo Pero Cartiglia, Nilesh Madhu

    Reliable solid-state nanopore sensing requires stable, low-noise ionic current baselines. Existing stability evaluation methods often rely on subjective visual inspection. Here, we propose a robust quantitative framework that assesses nanopore wettedness and stability indicators through power spectral density (PSD) analysis of the noise floor in the measured ionic current and uses the resulting features to predict wettedness. A systematic comparison of multiple PSD fitting models and weighting strategies identified a five-component, five-parameter (5C5P) model coupled with high-frequency, low-PSD (HFLS) weighting as the most accurate and consistent approach for characterizing noise in the measured ionic current. Utilizing the noise coefficients from this optimized noise PSD fit, we applied logistic regression to predict nanopore wettedness. Among these coefficients, the 1/f noise coefficient and the white-noise coefficient, together with a compact measure of overall low-frequency noise and the applied voltage, formed a compact and interpretable feature set for distinguishing wetted and unwetted pores. A logistic regression classifier trained on these features achieved high performance across a mixed-voltage dataset (median F1-score = 98%) and generalized effectively to unseen applied voltages and different pore dimensions. Segment-wise evaluation on one-second windows that mimic real-time operation demonstrated that the classifier reliably distinguished wetted and unwetted pores across all applied voltages. This physics-informed, data-driven framework enables automated wettedness prediction and stability assessment, indicating a pathway toward reliable real-time quality control for multiplexed, high-throughput solid-state nanopore sensing platforms.

    2026ACS omega(2026)引用:33
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    4Fundamental Understanding of Exposure and Process Chemistry of Sn-based Metal Oxide Resists: Effects of Ambient Environment During Post-Exposure Delay and Bake
    Ivan Pollentier,Fabian Holzmeier,Roberto Fallica, Ying-Lin Chen,Dhirendra P. Singh, Lorenzo Piatti,Hyo Seon Suh,Danilo De Simone,Stefan De Gendt,Paul Van Der Heide, John Petersen, Kevin Dorney

    Metal oxide resists (MORs) have shown great promise for high-resolution patterning in extreme ultraviolet (EUV) lithography, with potential for integration into high-volume manufacturing. However, MORs have recently been shown to exhibit sensitivity to process conditions and environment, leading to critical dimension (CD) variation. Although this variation can be reduced with proper process control, there is a current lack of fundamental knowledge on how these aspects affect the pattern formation mechanism. Moreover, the diverse composition of atmospheric environments makes it difficult to disentangle the role of individual atmospheric components on the lithographic performance of this promising class of EUV photoresists. To bridge these knowledge gaps, we deploy a coordinated, fundamentals-focused approach to yield deep insights into MOR exposure and process chemistry. Our results on a model MOR, an n-butyl Sn-Ox system, reveal how parameters such as exposure dose, post-exposure bake (PEB) temperature, and atmospheric environment influence the EUV exposure and post-exposure delay (PED) and PEB mechanisms. Using an advanced toolset, we show that EUV-induced ligand cleavage likely occurs via homolytic Sn-C bond breaking, resulting in a Sn-based radical "active site," which serves as a reactive center that endows MOR materials with their sensitivity to atmospheric components (e.g., H2O and O-2 ) during PED and PEB. We resolve the roles of H2O during PED and PEB, and in particular, we show that PEB environments containing O-2 exhibit increased litho performance (reduced dose and improved development contrast), suggesting that O-2 plays a critical role in the exposure and thermal mechanisms of MOR materials. Our results, and the coordinated approach using correlative spectroscopies, provide a strong foundation for understanding the critical EUV exposure and PED and PEB mechanisms in MOR materials, provide insights into potential optimization routes via environmental control during the process, and finally offer the potential to link mechanistic aspects and MOR lithographic performance and stability.

    2026JOURNAL OF MICRO-NANOPATTERNING MATERIALS AND METROLOGY-JM3(2026)引用:20
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    5Thermal Characterization of 650 V GaN HEMTs on 200 Mm Engineered Substrates
    Zequan Chen, James W. Pomeroy, Zeina Abdallah, Leo Norman, Peng Huang, Matthew D. Smith,Anurag Vohra, Sujit Kumar,Stefaan Decoutere,Benoit Bakeroot,Martin Kuball

    The thermal characteristics of large area GaN HEMTs on 200 mm QST engineered substrates are compared to those on GaN-on-Si. The thermal conductivity (TC) of the superlattice (SL) epitaxial buffer layers and the buried oxide layer (BOX) on the QST substrates are extracted through Raman thermography combined with 3-D finite element method (FEM) thermal simulations. The thermal resistance of large area transistors on QST is up similar to 1/3 lower than equivalent transistors on GaN-on-Si substrates. Transient device thermal simulation also demonstrates that QST substrates are advantageous for thermal management during switching operations, despite the buried oxide layer.

    2026IEEE ELECTRON DEVICE LETTERS(2026)引用:9
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    合作机构(100)

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    哈塞尔特大学合作论文 11
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