The increasing demand for high-voltage (>1200 V) power devices has driven the epitaxy of thick GaN buffers on top of mechanically robust substrates, such as engineered QST (R) substrates. This study investigates the material crystalline defects in vertical GaN buffers grown via metalorganic chemical vapor deposition on 200 mm QST (R), with and without pre-grown epitaxial lateral overgrown (ELOG) buffers. We present a systematic analysis of the threading dislocation density (TDD) using several destructive and non-destructive techniques such as transmission electron microscopy (TEM), cathodoluminescence (CL), electron channeling contrast imaging (ECCI), x-ray diffraction (XRD) and scanning probe microscopy (SPM). They reveal different dislocation types, i.e. edge, mixed and screw TDs. TEM reveals a similar to 5 times TDD reduction for stacks employing ELOG buffers. ECCI, CL and XRD complement one another with similar to 2-2.5 times reduced TDD on ELOG buffer. Whereas CL reveals all TDs involved in non-radiative recombination, ambiguity remains in ascribing the specific TD type. ECCI primarily identifies mixed TDs. XRD analyses of GaN(0002) and (10-12) reflections reveal a systematic improvement of crystal quality with increasing drift layer (DL) thickness. ELOG buffer reveals similar to 4 times stronger screw TD reduction and >6 times stronger edge TD reduction with increasing DL thickness, compared to the one without. Conductive atomic force microscopy measurements show that only similar to 0.1%-0.2% of the total TDs are electrically active contributing to vertical leakage, with >3 times reduction of such TDs in the ELOG buffer. Cross-sectional SPM, CL and ECCI imaging further validate the reduced defectivity in ELOG-enabled stacks. The scanning capacitance microscope (SCM) |dC/dV| maps show reduced amplitude at defect sites and CL imaging clearly visualizes these darker non-radiative recombination regions, whereas ECCI complements these observations. In summary, this study presents a comprehensive defectivity analysis of GaN-on-QST (R) substrates with ELOG buffers, demonstrating their potential for vertical GaN device fabrication and up-scaling.

In different architectures of GaN power devices, such as in vertical MOSFETs, where a p-type layer is present in between n-type layers or contacts, punch-through is one important aspect that limits high voltage operation. This is especially critical in architectures with a buried pGaN layer due to the difficulty in obtaining high acceptor concentrations. In this letter, it is shown that trap-assisted Space Charge Limited Conduction (SCLC) can cause anomalous current behavior and delayed device breakdown due to charge trapping in deep acceptor states where immediate destructive failure due to punch-through would otherwise be seen. While trap-assisted SCLC has been identified in vertical GaN p/n diodes before, no insight has been given so far on the nature of the deep trap states responsible for such behavior. Through electrical characterization and numerical simulations, it is shown that the most plausible physical origin for such deep acceptors are threading dislocations with an edge component, possibly with a 5/7 atom ring core structure. Moreover, it is demonstrated here that large charge screening around dislocations that arises from the low doping levels in such structures may compromise most or all of the active area, allowing electron capture by what would be otherwise highly localized trap states at the dislocation core.

The thermal characteristics of large area GaN HEMTs on 200 mm QST® engineered substrates are compared to those on GaN-on-Si. The thermal conductivity (TC) of the superlattice (SL) epitaxial buffer layers and the buried oxide layer (BOX) on the QST® substrates are extracted through Raman thermography combined with 3- D finite element method (FEM) thermal simulations. The thermal resistance of large area transistors on QST® is up ~1/3 lower than equivalent transistors on GaN-on-Si substrates. Transient device thermal simulation also demonstrates that QST® substrates are advantageous for thermal management during switching operations, despite the buried oxide layer.

The thermal characteristics of large area GaN HEMTs on 200 mm QST engineered substrates are compared to those on GaN-on-Si. The thermal conductivity (TC) of the superlattice (SL) epitaxial buffer layers and the buried oxide layer (BOX) on the QST substrates are extracted through Raman thermography combined with 3-D finite element method (FEM) thermal simulations. The thermal resistance of large area transistors on QST is up similar to 1/3 lower than equivalent transistors on GaN-on-Si substrates. Transient device thermal simulation also demonstrates that QST substrates are advantageous for thermal management during switching operations, despite the buried oxide layer.

The leakage conduction mechanisms in AlON dielectric deposited on GaN are identified and compared to the findings for Al2O3. Poole-Frenkel emission from similar trap energy levels was identified in both atomic layer deposited AlON and Al2O3, despite at different electric field ranges, while Fowler-Nordheim tunneling dominated the leakage current characteristics for Al2O3 at average electric field values. It is concluded that the differences observed in the leakage characteristics for these dielectrics are likely a result of the slightly larger conduction band offset between AlON and GaN. The identification of the same trap state energy level responsible for Poole-Frenkel emission in AlON and Al2O3 means that this trap state does not originate from the presence of nitrogen in the dielectric and is related to AlOx compounds and the deposition method. Bulk charge trapping is shown to play a major role in the leakage characteristics of AlON from average to high electric fields, which shifts the transfer characteristics from a certain electric field onward and causes hysteresis. These results provide valuable insights into the development of insulated gate architectures on GaN using the promising dielectric material AlON as the gate oxide.

This paper investigates gate-to-source (G-S) electrostatic-discharge (ESD) robustness in 650-V p-GaN Schottky-gate enhancement-mode (E-mode) power HEMTs. For forward G-S ESD, epitaxial splits including top spacer (TS) and bottom spacer (BS) with varying Al composition were fabricated and evaluated. Transmission-line-pulse (TLP) measurements reveal that the forward G-S ESD capability strongly depends on the BS, with increasing Al composition significantly enhancing the forward TLP current. In particular, introducing an AlN BS increases the forward TLP current by approximately 14 times compared with the BS-free structure, whereas the TS exhibits a comparatively minor impact. TCAD simulations and failure analysis indicate that the AlN BS effectively mitigates current crowding beneath the gate, consistent with the measured ESD improvement. For reverse G-S ESD, a proposed source-connected secondary field-plate (FP2) structure combined with reduced gate-to-source spacing (Lgs) enhances the TLP current capability, achieving robustness up to JEDEC HBM Class 1C for a device with Ron = 606 mΩ. The proposed solution introduces internal coupling capacitance without additional area penalty, strengthening transient discharge capability while reducing the channel depletion width and increasing the channel depletion capacitance.

This work investigates the dynamic switching characteristics of gated-edge termination (GET) Schottky barrier diodes (SBDs) fabricated on a 200-V GaN-on-SOI platform, with an emphasis on performance under continuous switching conditions. A wafer-level continuous-switching methodology is employed to characterize the dynamic on-resistance and forward voltage under varying switching frequencies (100–300kHz), duty cycles (30%–70%), off-state switching voltages (up to 200 V), and temperatures ( $25~^{\circ }$ C– $125~^{\circ }$ C). A capture-emission trapping model is used to extract time constants and explain the observed duty cycle- and temperature-dependent degradation behaviors. Through a systematic comparison of three field-plate configurations, the study reveals that an additional metal field plate effectively mitigates electric field crowding and trap occupation, which suppresses dynamic switching degradation. This work provides critical insights into the physical mechanisms governing degradation in AlGaN/GaN-based power SBDs, aiming to improve their dynamic switching stability.

Experimental data from gallium nitride (GaN)-on-Si p-GaN gate high-electron-mobility transistors (HEMTs) reveal a strong dependence of terminal capacitances-particularly C-BS, C-BG, and C-BD-on the drain-to-source voltage (V-DS), indicating significant coupling through the bulk contact. This behavior, linked to progressive depletion of the 2-D electron gas (2DEG) under field plates, is not adequately captured by existing compact models. This work presents a detailed analysis of the dynamics of V-DS-dependent depletion under field plates and develops an enhanced MIT Virtual Source GaN FET (MVSG) compact model that incorporates bulk-related capacitance contributions. The proposed model introduces a depletion-dependent modulation of channel and fringing capacitances and captures channel length modulation (CLM) effects due to progressive depletion of 2DEG with increasing V-DS. The extended model shows excellent agreement with the measured capacitance behavior and provides a deeper understanding of the substrate interaction mechanisms. This advancement supports the design of next-generation high-voltage GaN power ICs, such as integrated half-bridges and gate drivers, by enabling accurate prediction of terminal capacitances in simulations that include substrate effects.

Charge transport in 650-V-rated GaN high electron mobility transistors (HEMTs) was investigated using positive substrate bias up to +600 V. Positive substrate bias resulted in a reduction in channel current, attributed to negative charge storage in the buffer, resulting in up to a >50% reduction in the 2-D electron gas (2DEG) channel density. The dynamics of the accumulated charge was investigated using recovery transients after substrate bias stress, with recovery times >1000 s for substrate stress bias $>+$200 V. The recovery time was reduced significantly with the application of a negative substrate bias of short duration, immediately following the positive substrate bias stress. A comprehensive explanation is presented, which requires a detailed understanding of the transport (both ohmic and non-ohmic) through each of the layers in the epitaxial stack.

In this letter, we report an approach to improve the forward bias gate reliability of Schottky gate p-GaN HEMTs. In particular, a gate layout solution, namely Gate Within Active Area (GWA), aimed at improving the high-temperature time to failure (TTF), is proposed and validated. This solution allows to avoid the exposure of the gate finger (p-GaN/metal) to the nitrogen-implantation needed for termination and isolation purposes. GWA devices feature a significantly improved gate reliability at high temperature with respect to the reference ones, under both DC and pulsed stress tests. Finally, it is demonstrated that the Schottky gate p-GaN HEMTs show a positive temperature-dependent gate TTF in a range up to 150 °C, confirming the crucial role of impact ionization on the gate failure.

To make vertical GaN-based trench gate MOSFET devices commercially manufacturable, 200 mm engineered substrates with a poly-AlN core are a good substrate choice. The poly-AlN core, matched in thermal expansion to GaN, allows to grow high-quality thick GaN layers. Up to 11 $\mu$ m-thick GaN stacks were grown crack-free, with excellent control over the wafer warp. Breakdown values of 900 V were reached for the vertical p/n-junction. Full device processing was completed in a CMOS-compatible pilot line without any wafer breakage, demonstrating the mechanical strength of these substrates. On module level, a new gate trench profile combining a smooth sidewall and round corners, is presented. While a smooth sidewall is important for the ON-state performance of the devices, the rounded corners are beneficial for the OFF-state operation. A semi-vertical test vehicle was used to demonstrate the ON-state of the fabricated power transistors. For devices with an effective gate width ( $\textit{W}_{\text{G,\text{ef}\text{f}}}\text{)}$ of 180 mm and an active area of 1.4 mm $^{\text{2}}$ , an ON-state resistance could be achieved of 8 m $\Omega\cdot \text{cm}^{\text{2}}$ . By scaling the source contact length down, the device footprint could be decreased further. It is shown that for devices with a $\textit{W}_{\text{G,\text{ef}\text{f}}}$ of 60 mm this value could be further improved with best performing devices showing a 6.2 m $\Omega\cdot\text{ cm}^{\text{2}}$ ON-state resistance.

This paper deals with the defect study of a monolithically integrated GaN power transistor on a conductive Si substrate by Deep Level Transient Fourier Spectroscopy method (DLTFS). Due to the high non-exponentiality of measured capacitance transients we focused only on defects that were determined with high certainty in the investigated samples and confirmed by measurements under different conditions. Parameters of six electrically active defects with activation energies 0.28, 0.53, 0.81, 0.92, 0.09 a 0.84 eV were determined. The origin of these defects probably corresponds to dislocation extended from the GaN separating layer to the AlGaN layer, nitrogen point defects (vacancies and interstitials) or dislocations. We observed that the signal significantly increases in the low-temperature range at positive reverse voltages.

The forward bias gate leakage current and forward gate breakdown voltage are important properties of p-GaN gate high-electron-mobility transistors (HEMTs). An engineered doping profile in the p-GaN layer results in a higher gate breakdown voltage and a lower forward bias gate leakage current. The use of such a technique puts additional requirements on the compact models that are used for these p-GaN gate HEMTs. An accurate compact model is needed, which considers a change in the doping profile in the p-GaN layer of these devices. This article reviews the relationship between the gate bias and the voltage drops at the different junctions in the gate structure (i.e., at the metal/p-GaN Schottky junction and the p-GaN/AlGaN/GaN junctions) considering an engineered doping profile. This relationship is then used to model the drain-source current (I-DS) and gate leakage current (I-G). Three different regimes in the gate current have been considered in the model: Poole-Frenkel (PF) under low bias, thermionic emission (TE) in the medium bias range, and thermally assisted tunneling (TAT) at higher bias.

This article discusses the electrical stability of MOS structures on n-and p-type GaN for two different dielectrics, AlON and Al2O3, deposited by atomic layer deposition (ALD). Threshold voltage hysteresis was evaluated by means of capacitance-voltage (C-V ) double sweep measurements, performed on MOS capacitors. MOS structures on p-doped GaN show up to two orders of magnitude higher effective trapped charge density than on n-GaN. Moreover, AlON results in 10 times less trapped charge than Al 2 O 3 on p-GaN. The leakage current is also identified as an important factor in defining the electrical stability at high electric fields, due to the enhanced injection of electrons into the MOS stack. Electron trapping is shown to happen either at the dielectric-semiconductor interface or in border traps. AlON results in lower flat-band and threshold voltages likely due to the resulting fixed interface charge from surface reconstruction. The effect of the n-type doping density as well as of dry etch damage on the effective trapped charge after injection has been shown to be minimal. These results are important for different insulated gate device architectures. We show that extremely low threshold voltage hysteresis values can be reached in a trench-shaped gate GaN MOSFET using AlON as an interface dielectric.

Time-dependent conduction in epitaxial superlattice (SL) strain relief layers of GaN high electron mobility transistors on 200 mm engineered substrates with a poly-AlN core was observed and analyzed. This phenomenon occurs when the devices were operated with substrate bias of ∼−300 V for 101–103 s. The formation of the conduction path is related to trap-assisted leakage through the SLs on the engineered substrates; de-trapped carriers spread out vertically and laterally within a portion of the SLs, leading to a higher electrical field across the rest of the layers. This conduction mechanism may be hidden during the devices' normal operation (target 650–1200 V). It could lead to undesired effects during the operation of the devices, such as a time-dependent dynamic Ron. More resistive SLs will potentially reduce the impact of this phenomenon.

In this work, a random telegraph noise (RTN) analysis has been carried out, to the best of our knowledge, for the first time to characterize the defects activated by forward-biased gate stress in GaN-HEMTs with metal/pGaN Schottky gate. The RTN signal has been measured for both gate leakage (I G ) and drain current (I D ), after each stress phase until the occurrence of the time-dependent gate breakdown. By analyzing the power spectral density (PSD) of post-stress currents, four 1/f 2 components, featuring different amplitude and time constants, were observed. In contrast, the PSD derived from fresh currents does not display segments with 1/f 2 trend. Three RTN components have been observed on both I G and I D , suggesting defect/s in the AlGaN barrier or at the AlGaN/GaN interface, whereas the fourth one showed up only on I G , could be possibly related to defects at the Schottky junction.

This letter experimentally demonstrates 1.2 kV normally-off p-GaN gate lateral high-electron-mobility transistors (HEMTs) on 200 mm diameter engineered substrates. The fabricated p-GaN gate HEMT with optimum gate-drain spacing exhibits a threshold voltage (V-th) of 3.2 V, an ON/OFF ratio of 108, low specific ON-resistance (R-on,R-sp) of 5.8 m Omega-cm(2) and hard breakdown voltage (V-bd) at 1800 V. Optimized devices also show good wafer scale uniformity ( sigma(Ron) =1.2% ) for the evaluated electrical parameters and passed on-wafer high temperature gate bias (HTGB) and reverse bias stress tests without device failures.

The effectiveness of GaN-IC technology for power electronics depends on the seamless integration of high-power devices and peripheral circuits. Peripheral circuitry architecture dictates performance and competitiveness. The absence of a well-performing p-type device compels adoption of resistor-transistor logic (RTL) and direct-coupled field effect transistor logic (DCFL) architectures for analog building blocks in designing fully integrated GaN-IC circuits. It is therefore crucial to evaluate the trade-offs of each architecture. This paper analyzes the performance of three inverter architectures in a GaN-IC platform: one type is based on RTL and two other types based on DCFL. In addition to the enhancement mode (E-mode) high-electron-mobility transistor (HEMT) as the driver, the RTL architecture uses a 2-Dimensional Electron Gas (2DEG) layer as resistor load, whereas the DCFL architecture uses a gate-source shorted depletion mode (D-mode) HEMT as the load. There are two choices for the D-mode device: the D-mode metal-insulator-semiconductor (MIS) HEMT and the D-mode pGaN island HEMT. For a thorough comparison, key performance metrics such as noise margins, rise/fall times, average power consumption, propagation delay, threshold voltage, and the architectures’ footprint are analyzed. The trade-offs of each architecture are analyzed by varying the size of driver and load devices to understand their effect on the various inverter performance metrics. Understanding these metrics and their relationship with device parameters aids in selecting the most suitable architecture for intended application.

This work addresses the impact of the Mg activation anneal step and the resulting acceptor concentration on the channel mobility and VT stability of vertical MOSFETs. Increasing the annealing time with N2 only ambient and the annealing temperature with O2 in the ambient is shown to be effective in increasing the channel acceptor concentration. When the effective acceptor concentration is increased, the mobility is degraded due to a transition in the main scattering mechanism from Coulomb to surface roughness scattering. Degradation of the on-state current and maximum transconductance at high operating temperatures was linked to bulk mobility degradation of the drift layer due to lattice scattering. The two Mg activation annealing conditions considered here show different trends with regard to the threshold voltage stability, while N2 only ambient did not impact this parameter, including O2 increased threshold voltage instability. It is shown that increasing the Mg chemical concentration in the p-GaN layer degrades channel mobility and threshold voltage stability, irrespectively of the effective acceptor concentration, providing evidence for degradation of the channel/dielectric interface characteristics with higher Mg chemical concentration. This study shows that it is possible to achieve very low threshold voltage hysteresis and high channel mobility by reducing the Mg chemical concentration while maintaining high effective acceptor concentration. These results provide key insights for the development of vertical GaN FETs.

This article is about the study and characterization of a monolithically integrated dual-gate bidirectional switch (BDS) realized in a CMOS-compatible gallium nitride (GaN) pilot line. The switch is based on a p-GaN gate enhancement-mode (E-mode) high-electron-mobility transistor (HEMT) rated for 650 V and provides a symmetrical electrical operation in positive and negative bias conditions while achieving comparable performance to the traditional HEMT and, with respect to the implementation of conventional BDSs, the overall ON-resistance is sensibly lower. Several layout variations are discussed both through the electrical measurements and technology CAD (TCAD) simulations, together with comparisons with the reference HEMT, providing valuable insights into the design optimization of dual-gate BDSs.