Indian Institute of Information Technology Una

Latent fingerprinting has significantly evolved and improved from the advances in Artificial intelligence. Though AI has played a pivotal role in overcoming latent fingerprint recognition challenges, however, its illicit application cannot be neglected. The paper presents fundamentals of latent fingerprinting and a review of AI-based latent fingerprint systems with a focus on loopholes exploited by adversaries for attacking the AI-based systems. The subsequent sections of the paper are organized around the five research questions, with each section presenting a focused review, critical discussion, and potential future direction. These research questions are designed to comprehensively address diverse dimensions related to technical, ethical and the deployment aspects, to ensure practical relevance and theoretical depth of the domain. Further, a discussion on the specifications of benchmark latent fingerprint datasets along with the methods for synthetic fingerprint generation using AI has been presented. The existing drawbacks, challenges and corresponding solutions are presented suggesting the usage of explainable and responsible AI concepts in latent fingerprinting. As a result, the present paper opens opportunities suggesting potential fingerprinting tools and intelligent approaches which assist in building secure, reliable and robust recognition systems. The paper has put forward the concept of integrating security and AI in latent fingerprinting in doublefold manner, i)synthetic fingerprints data generation and ii) recognition of the data with explainability for commercial viability of the models. In future, the objective is to use emerging technologies like Quantum AI, federated learning, edge computing etc., to build responsible and robust fingerprint recognition systems.

Microbial diversity and sustainable agriculture are key players for the mutual harmony of the nature/agriculture ecosystem that align with the Sustainable Development Goals (SDGs). However, to harness their best potential, it is necessary to understand the complex interactions between microbial communities and plants. This has become feasible with the intervention of advanced multiomics techniques including genomics, metagenomics, transcriptomics, proteomics, metabolomics, etc. With the advent of next-generation technologies, production of biological data at a cost-effective expense has escalated rapidly. Thus, it is feasible for all researchers to explore these advanced technologies for a better understanding of how to harness the full potential of microbial diversity toward sustainable agriculture. The growth of biological databases, particularly microbial databases, and interphasic tools are bound to the rapid growth of bioinformatics domains. Additionally, bioinformatics provides the direction for better understanding of the interaction of the microbe–plant system. Keeping in view the expansion of escalated biological datasets, the role of big data analytics is vital to understand the interplay of the diverse datasets along with the growing biological databases. The relevant case studies employing big data analytics in sustainable agriculture have been discussed. This will help to make better decisions toward the productivity of sustainable agriculture. This review is an attempt to showcase the recent growth of bioinformatics databases and the role of big data analytics in achieving sustainable agriculture.

Change detection (CD) in remote sensing aims to identify semantic differences between satellite images captured at different times. While deep learning has significantly advanced this field, existing approaches based on convolutional neural networks (CNNs), transformers and Selective State Space Models (SSMs) still struggle to precisely delineate change regions. In particular, traditional transformer-based methods suffer from quadratic computational complexity when applied to very high-resolution (VHR) satellite images and often perform poorly with limited training data, leading to under-utilization of the rich spatial information available in VHR imagery. We present GRAD-Former, a novel framework that enhances contextual understanding while maintaining efficiency through reduced model size. The proposed framework consists of a novel encoder with Adaptive Feature Relevance and Refinement (AFRAR) module, fusion and decoder blocks. AFRAR integrates global-local contextual awareness through two proposed components: the Selective Embedding Amplification (SEA) module and the Global-Local Feature Refinement (GLFR) module. SEA and GLFR leverage gating mechanisms and differential attention, respectively, which generates multiple softmax heaps to capture important features while minimizing the captured irreverent features. Multiple experiments across three challenging CD datasets (LEVIR-CD, CDD, DSIFN-CD) demonstrate GRAD-Former's superior performance compared to existing approaches. Notably, GRAD-Former outperforms the current state-of-the-art models across all the metrics and all the datasets while using fewer parameters. Our framework establishes a new benchmark for remote sensing change detection performance. Our code will be released at: https://github.com/Ujjwal238/GRAD-Former

The rapidly advancing domain of visible light communication (VLC) technology is immensely recognized as a potential adjunct to prevailing radio frequency (RF) systems, utilizing optical orthogonal frequency division multiplexing (OOFDM) to achieve superior data transmission rates, thereby aligning with the stringent requirements of 5G standards. Nevertheless, notwithstanding its substantial benefits, the inherent multicarrier architecture of OOFDM engenders constructive interference at certain subcarrier intervals in inverse fast fourier transform (IFFT) operation, thereby exacerbating the peak-to-average power ratio (PAPR). Among the plethora of PAPR reduction techniques, non-distorting methods such as selective mapping (SLM) have been unequivocally established as the most efficacious in attenuating the inevitably severe PAPR. However, the proliferation of candidate alternatives significantly escalates computational complexity, thereby presenting a formidable challenge in the practical application of SLM. To mitigate this complexity, the proposed methodology entails the multiplication of phase sequence vectors at a specific intermediate stage of the IFFT, thereby facilitating the generation of candidate signals. This novel approach results in a pronounced reduction in PAPR when compared to the conventional CSLM technique. Furthermore, the conjugate symmetry property of the first-stage IFFT output contributes to an additional reduction in PAPR, enhancing the overall efficacy of the system. The DCO-OFDM signal exhibiting the minimum PAPR across all candidates is selected for transmission, thereby optimizing the performance. Through rigorous complexity analysis and extensive simulation results, it is conclusively demonstrated that this innovative complexity reduction strategy not only surpasses the conventional CSLM method but also offers a promising solution for seamless integration into future-generation VLC systems.

Modern processors need to handle a large number of instructions efficiently. Executing them one after another often leads to longer delays and reduced system performance. Pipelining helps overcome this limitation by allowing different stages of multiple instructions to run at the same time. As one instruction is being executed, the next can already be fetched or decoded, which improves overall speed and utilization. Among various architectures, RISC-based processors are generally preferred for pipelined designs because of their simpler instruction sets and reduced dependency between instructions. Nevertheless, pipelined systems also have to deal with issues like data and control hazards, which can disrupt the flow of instructions and lower efficiency. This work uses Verilog HDL to design and develop a 32-bit five-stage pipelined RISC-V processor. To reduce delays brought on by pipeline hazards, the design incorporates strategies like branch prediction, stall control, and data forwarding. In addition to the M and F extensions for multiplication, division, and floating-point operations, it supports the RV32I base instruction set. To increase throughput, the processor has a Harvard design with distinct instruction and data memory. The single-cycle implementation of the processor operates at a maximum frequency of 31.6 MHz, while the pipelined version achieves 87.86 MHz—about 2.8 times faster. The frequency increases to 90.2 MHz with optimized hazard-handling and a 4% decrease in power consumption. Additionally, its modular design makes it simple to add custom instructions and scale. Because of these characteristics, the suggested processor is ideal for embedded and Internet of Things applications where both high performance and low power consumption are crucial.