Jharkhand Rai University is a private university in Ranchi, Jharkhand state, India. The university is located in Kamre, Ratu Road, Ranchi. It was established by the Jharkhand State Legislature under the Jharkhand Rai University Act, 2011.
This paper addresses the trajectory-tracking problem for discrete-time linear time-invariant systems with bounded parametric uncertainty, subject to hard constraints on system states, control inputs, and input rates. Unlike existing methods, which often consider only partial uncertainty, omit input-rate or state constraints, or focus on regulation problems, this work provides a systematic adaptive model predictive control (MPC) solution for constrained trajectory tracking under full parametric uncertainty. Determining the control input required to achieve zero tracking error under unknown parameters is challenging. Simultaneously, trajectory tracking under uncertainty with input-rate constraints induces temporal coupling in the control sequence, resulting in a time-varying admissible control set and rendering standard recursive feasibility arguments inapplicable. These challenges are overcome by systematically utilizing the estimated system parameters, coupled with a suitably designed adaptive learning process within a reformulated MPC framework. The recursive feasibility of the proposed MPC optimization routine is then rigorously established despite the time-varying admissible control set induced by input-rate constraints. Closed-loop stability is guaranteed via Lyapunov-based analysis, ensuring convergence of the tracking error and boundedness of system states. Simulation results validate the effectiveness of the pr
In this paper a low-power dynamic CMOS comparator designed in 45nm and 180nm technology with a capability of operation at any voltage level. New circuit design techniques are being implemented for optimum performance, which include the Leakage Control Transistor (LECTOR) and Gate Leakage Transistor (GALEOR). By incorporating leakage-control transistors in active-high (PUP) and active-low (PDN) networks, much of the critical path gets eliminated, and leakage current gets well reduced when compared to normal designs. Our technique employs a massive number of transistors operated in the off-state to minimize power consumption. For this reason, the proposed comparator is evaluated in terms of power dissipation and delay, and it improves enormously on previous solutions. This paper is a deep dive into the designs of both LECTOR and GALEOR comparators for their considerable contribution to power and delay optimization. LECTOR strikes a finely tuned balance on power consumption reduction, consuming between 13 and 23% less while keeping up good results for delay, especially at higher voltage levels. GALEOR, however, is much better at power efficiency, showing more than 96% savings and thus making it the best choice for ultra-low-power applications. Together, these designs present promising strategies for enhancing efficiency in the current electronics world regarding different applications in power-sensitive and performance-oriented embodiments.
The need for new skill sets has increased as Artificial Intelligence (AI) continues to transform the modern workplace, forcing businesses and academic institutions to reevaluate their workforce development plans. The pressing need for upskilling and reskilling in response to AI integration across industries is examined in this article. AI is rapidly enhancing human functions rather than taking their place, creating a hybrid model where cooperation between humans and AI is the norm. In addition to being digitally savvy, this change calls for a workforce that possesses critical thinking, adaptability, and creative problem-solving skills. The article will focus on the changing skill requirements brought about by the deployment of AI, emphasizing the major industries most impacted by the change. Additionally, it will examine effective frameworks and tactics used by progressive governments and companies to prepare their workforce for the future. Continuous learning ecosystems, micro-credentialing, and public-private collaborations that promote lifetime learning will be prioritized.
This paper presents the RTL design logic of vending machine and its implementation into FPGA zed board. FPGA technology enables faster processing, reconfigurability, and better resource efficiency for vending control. The FPGA-based approach provides a modern, adaptable, and high-performance solution for vending machine automation. The Control logic in this proposed model of vending machine includes insertion of amount, cancel operation and dispensing of candy. The proposed design is tested and simulated using Xilinx Vivado 2024 version, achieving a 69.3% of power optimization than the previous model, with further power consumption and timing analysis performed across different RTL coding styles (if-else, switch case, and while loop implementations).
Traditional programming interpreters are primarily designed to perform lexical analysis, syntax analysis, semantic processing, and program execution according to predefined programming-language rules. Although such interpreters provide reliable and deterministic execution, they generally have limited capabilities for contextual code understanding, adaptive optimization, intelligent assistance, and continuous security analysis. Recent advances in artificial intelligence (AI), large language models (LLMs), machine learning (ML), and cloud computing provide an opportunity to transform conventional interpreters into intelligent execution environments. However, integrating AI directly into an interpreter introduces additional concerns related to malicious code execution, vulnerable AI-generated code, prompt injection, data exposure, model manipulation, privacy, and computational overhead. This paper proposes an AI-Powered Secure Intelligent Interpreter (AISII) that integrates conventional interpretation mechanisms with AI-based code understanding, vulnerability analysis, runtime behavioral monitoring, anomaly detection, secure sandboxing, adaptive policy enforcement, and cloud-assisted intelligence. The proposed architecture follows a modular, defense-in-depth approach in which source code is analyzed through lexical, syntactic, semantic, static-security, and AI-based assessment stages before execution. A runtime monitoring layer continuously evaluates execution behavior and dynamically updates a risk score. Depending on the estimated risk, the security policy engine can permit, restrict, isolate, or terminate execution. The framework further incorporates local, edge, and cloud intelligence to balance privacy, latency, and computational scalability. A comparative analysis positions the proposed architecture against conventional interpreters, AI-assisted programming tools, static analysis systems, and autonomous software-engineering agents. An experimental methodology is also proposed using code-generation benchmarks, vulnerability datasets, benign/malicious execution workloads, and real-world software-engineering tasks. Evaluation metrics include execution latency, resource utilization, vulnerability-detection precision, recall, F1-score, false-positive rate, and containment effectiveness. The paper concludes with an implementation roadmap and discusses federated learning, edge AI, autonomous programming, and quantum computing as future research directions. The proposed framework provides a foundation for developing interpreters that are not merely execution engines but adaptive, intelligent, and security-aware computing environments.
