Micro Electronics, Inc. (MEI) is an American privately owned corporation headquartered in Hilliard, Ohio. Founded in 1979 by John Baker, it serves as the parent company of the computer retailer Micro Center, its online division Micro Center Online, and its brand iPSG, which houses PowerSpec PC, WinBook, and Inland(including Inland Premium for high-end SSDs)..
In principle BB84 protocol supports secure quantum communication by assuming transmitter and receiver devices to be ideal. However, practically it is very challenging to build an ideal single photon source and detector. These imperfections in practical devices (i.e., wavelength mismatch, full width at half maximum (FWHM) pulse width mismatch and different arrival times of photon) leads to side channel attacks. In this work, we have analyzed the wavelength mismatch issue associated with four laser diode based practical BB84 transmitter. An asymptotically achievable rate of extraction of secure key (also known as key generation rate) is estimated from side-channel leakage calculation between transmitter (Alice) and adversary (Eve).
An efficient method is developed to estimate the load level at which a crack occurs on the constituent fiber/matrix interface of a composite subjected to any load. Only the original properties of the fiber and matrix documented in advance or measured independently are required for this estimation, in addition to the transverse tensile strength of a unidirectional (UD) composite made from the same constituent system. Stress concentration factors (SCFs) of the matrix in the composite are crucial for this purpose. Such an SCF cannot be defined following a classical approach, and the SCFs with the perfect and cracked interfaces are derived respectively. Letting the predicted transverse tensile strength of the UD composite with an initial perfect and later cracked interface be equal to the measured counterpart, a critical Mises stress of the matrix at which the crack occurs is obtained. When a Mises stress of the matrix in any other composite made of the same constituents approaches the critical value, the interface cracking load is determined accordingly. Given a fiber and matrix system, whether any further interface modification is necessary and how much potential exists for doing such can be easily understood.
In this paper, we investigate how to enhance an existing software-defined framework to reduce overheads and enable the parallel utilization of all the programmable processing resources present in systems that include FPGA-based hardware accelerators. To remove overheads, a new hardware platform is created based on interrupts, which removes spin-locks and frees the processing resources. Additionally, instead of simply using the hardware accelerator to offload a task from the CPU, we propose a scheduler that dynamically distributes the tasks among all the resources to minimize load unbalance. The experimental evaluation shows that the interrupt-based heterogeneous platform increases performance by up 22% while reducing energy requirements by 15%. Additionally, we measure between 50% to 25% reduction in execution time when the CPU cores assist FPGA execution at the same level of energy requirements depending on hardware speed-ups.
There is growing interest in lowering the energy consumption of computation. Energy transparency is a concept that makes a program's energy consumption visible from software to hardware through the different system layers. Such transparency can enable energy optimizations at each layer and between layers, and help both programmers and operating systems make energy aware decisions. The common methodology of extracting the energy consumption of a program is through direct measurement of the target hardware. This usually involves specialized equipment and knowledge most programmers do not have. In this paper, we examine how existing methods for static resource analysis and energy modeling can be utilized to perform Energy Consumption Static Analysis (ECSA) for deeply embedded programs. To investigate this, we have developed ECSA techniques that work at the instruction set level and at a higher level, the LLVM IR, through a novel mapping technique. We apply our ECSA to a comprehensive set of mainly industrial benchmarks, including single-threaded and also multi-threaded embedded programs from two commonly used concurrency patterns, task farms and pipelines. We compare our ECSA results to hardware measurements and predictions obtained based on simulation traces. We discuss a number of application scenarios for which ECSA results can provide energy transparency and conclude with a set of new research questions for future work.
