Micro Electronics, Inc.

In principle BB84 protocol supports secure quantum communication by assuming transmitter and receiver devices to be ideal. However, practically it is very challenging to build an ideal single photon source and detector. These imperfections in practical devices (i.e., wavelength mismatch, full width at half maximum (FWHM) pulse width mismatch and different arrival times of photon) leads to side channel attacks. In this work, we have analyzed the wavelength mismatch issue associated with four laser diode based practical BB84 transmitter. An asymptotically achievable rate of extraction of secure key (also known as key generation rate) is estimated from side-channel leakage calculation between transmitter (Alice) and adversary (Eve).

An efficient method is developed to estimate the load level at which a crack occurs on the constituent fiber/matrix interface of a composite subjected to any load. Only the original properties of the fiber and matrix documented in advance or measured independently are required for this estimation, in addition to the transverse tensile strength of a unidirectional (UD) composite made from the same constituent system. Stress concentration factors (SCFs) of the matrix in the composite are crucial for this purpose. Such an SCF cannot be defined following a classical approach, and the SCFs with the perfect and cracked interfaces are derived respectively. Letting the predicted transverse tensile strength of the UD composite with an initial perfect and later cracked interface be equal to the measured counterpart, a critical Mises stress of the matrix at which the crack occurs is obtained. When a Mises stress of the matrix in any other composite made of the same constituents approaches the critical value, the interface cracking load is determined accordingly. Given a fiber and matrix system, whether any further interface modification is necessary and how much potential exists for doing such can be easily understood.

In this paper, we investigate how to enhance an existing software-defined framework to reduce overheads and enable the parallel utilization of all the programmable processing resources present in systems that include FPGA-based hardware accelerators. To remove overheads, a new hardware platform is created based on interrupts, which removes spin-locks and frees the processing resources. Additionally, instead of simply using the hardware accelerator to offload a task from the CPU, we propose a scheduler that dynamically distributes the tasks among all the resources to minimize load unbalance. The experimental evaluation shows that the interrupt-based heterogeneous platform increases performance by up 22% while reducing energy requirements by 15%. Additionally, we measure between 50% to 25% reduction in execution time when the CPU cores assist FPGA execution at the same level of energy requirements depending on hardware speed-ups.

There is growing interest in lowering the energy consumption of computation. Energy transparency is a concept that makes a program's energy consumption visible from software to hardware through the different system layers. Such transparency can enable energy optimizations at each layer and between layers, and help both programmers and operating systems make energy aware decisions. The common methodology of extracting the energy consumption of a program is through direct measurement of the target hardware. This usually involves specialized equipment and knowledge most programmers do not have. In this paper, we examine how existing methods for static resource analysis and energy modeling can be utilized to perform Energy Consumption Static Analysis (ECSA) for deeply embedded programs. To investigate this, we have developed ECSA techniques that work at the instruction set level and at a higher level, the LLVM IR, through a novel mapping technique. We apply our ECSA to a comprehensive set of mainly industrial benchmarks, including single-threaded and also multi-threaded embedded programs from two commonly used concurrency patterns, task farms and pipelines. We compare our ECSA results to hardware measurements and predictions obtained based on simulation traces. We discuss a number of application scenarios for which ECSA results can provide energy transparency and conclude with a set of new research questions for future work.

In this report we present a network-level multi-core energy model and a software development process workflow that allows software developers to estimate the energy consumption of multi-core embedded programs. This work focuses on a high performance, cache-less and timing predictable embedded processor architecture, XS1. Prior modelling work is improved to increase accuracy, then extended to be parametric with respect to voltage and frequency scaling (VFS) and then integrated into a larger scale model of a network of interconnected cores. The modelling is supported by enhancements to an open source instruction set simulator to provide the first network timing aware simulations of the target architecture. Simulation based modelling techniques are combined with methods of results presentation to demonstrate how such work can be integrated into a software developer's workflow, enabling the developer to make informed, energy aware coding decisions. A set of single-, multi-threaded and multi-core benchmarks are used to exercise and evaluate the models and provide use case examples for how results can be presented and interpreted. The models all yield accuracy within an average +/-5 % error margin.

Many scientific codes consist of memory bandwidth bound kernels — the dominating factor of the runtime is the speed at which data can be loaded from memory into the Arithmetic Logic Units. Generally Programmable Graphics Processing Units (GPGPUs) and other accelerator devices such as the Intel Xeon Phi offer an increased memory bandwidth over CPU architectures. However, as with CPUs, the peak memory bandwidth is often unachievable in practice and so benchmarks are required to measure a practical upper bound on expected performance. We present GPU-STREAM as an auxiliary tool to the standard STREAM benchmark to provide cross-platform comparable results of achievable memory bandwidth between multiand many-core devices. I. MEASURING MEMORY BANDWIDTH The STREAM Benchmark [1] measures the time taken for each of four simple kernels to be run (α is a scalar constant): 1) Copy: c[i] = a[i] 2) Multiply: b[i] = αc[i] 3) Add: c[i] = a[i] + b[i] 4) Triad: a[i] = b[i] + αc[i] It is simple to calculate how many bytes each of these kernels requires to be read from and written to memory, assuming perfect caching. Let β be the number of bytes to represent one element — for double precision β = 8. For an array of length N , copy and multiply move 2Nβ bytes, and add and triad move 3Nβ bytes. The ordering of the kernels ensures caches are invalidated, and as long as the arrays are large enough the data must be reloaded from main memory. The achieved sustained memory bandwidth can be found by dividing these numbers by the time to execute the corresponding kernel. GPU-STREAM implements these kernels in both the OpenCL and CUDA programming frameworks. This allows the benchmark to be used across a wide range of hardware from a wide range of vendors.

Power constraints are forcing HPC systems to continue to increase hardware concurrency. Efficiently scaling applications on future machines will be essential for improved science and it is recognised that the “flat” MPI model will start to reach its scalability limits. The optimal approach is unknown, necessitating the use of mini-applications to rapidly evaluate new approaches. Reducing MPI task count through the use of shared memory programming models will likely be essential. We examine different strategies for improving the strong-scaling performance of explicit Hydrodynamics applications. Using the CloverLeaf mini-application across multiple generations of Cray platforms (XC30, XK6 and XK7), we show the utility of the hybrid approach and document our experiences with OpenMP, CUDA, OpenCL and OpenACC under both the PGI and CCE compilers. We also evaluate Cray Reveal as a tool for automatically hybridising HPC applications and Cray’s MPI rank to network topology-mapping tools for improving application performance.

Robotic assistants are being developed to assist with a range of tasks at work and home. Besides designing and developing such robotic assistants, a key issue that needs to be addressed is showing that they are both safe and trustworthy. We discuss our approach to this using formal verification, simulation-based testing and formative user evaluation.