意法半导体

The key technical challenge in developing high-performance micro-energy storage systems based on thin films that offer enhanced rate performance and cycling stability is to find low-energy, time-consuming methodologies for depositing thick, conformal films on complex 3D architectures. This work addresses this challenge by presenting a chemical solution deposition approach based on spin coating, which can deposit WO3 thin films with a thickness ranging from 100 to 500 nm on high-aspect-ratio 3D silicon substrates. Combining an optimized 3D substrate with a high AEF and an optimized film thickness results in the electrodes exhibiting a 30-fold increase in capacity compared to 2D planar counterparts, in line with the area enlargement factor. Electrochemical evaluations demonstrate stable capacity of 320 & micro;Ah cm(-2), even when the potential is limited to prevent conversion reactions. Furthermore, a capacity of 82 & micro;Ah cm(-2) is retained at a high current density of 500 & micro;A cm(-2). The improved rate capability is attributed to the expanded surface area of the 3D electrode, the reversible Li + intercalation mechanism and the nanoscale WO3 structure, which minimize Li ion paths.

The crystallization of initially amorphous Ge-rich Ge-Sb-Te nanostructures is investigated using fast thermal pulse heating, coupled with in situ scanning transmission electron microscope-energy dispersive spectroscopy (STEM-EDX) and high resolution (HR)-Transmission electron microscopy (TEM) analyses. Chemical analysis reveals a Te-Ge interdiffusion mechanism occurring at the bottom interface between the Ge-rich GST (GGST) layer and the underlayer (UL). The initially Ge-rich cell shows increasing Te-enrichment as the temperature increases. The onset of crystallization was found to start at 350 degrees C with pure cubic Ge grains appearing first, followed by cubic GST at 390 degrees C. Initially localized at the interfaces, the crystallization of both phases spreads heterogeneously throughout the cell. The spatial distribution of grains is compared with the variations in chemical composition at the nanometric scale.

Fully Depleted Silicon-On-Insulator (FD-SOI) technology continues to evolve, driven by the need to enhance carrier mobility through innovative channel engineering. This involves, in particular, replacing silicon with SiGe alloys, and introducing controlled compressive strain to improve the performances of both nMOS and pMOS transistors. However, conventional approaches employing Si1-xGex pseudo-substrates on silicon remain constrained by Ge concentrations not exceeding 30 % and dislocation densities typically around 10(6 )cm(-2) which limit further performance gains. In this study, we address these limitations by developing a methodology aimed at increasing the Ge concentration in SiGe layers while suppressing defect formation. Our approach combines epitaxial growth with subsequent Ge condensation on SOI substrates, implemented on 300 mm wafer and under industrial process conditions. We demonstrate that initiating the process with a similar to 20 nm-thick epitaxial SiGe layer containing similar to 20 % Ge is critical for ensuring high structural quality during the high temperature condensation step. This optimized strategy leads to the formation of Ge-rich SiGe pseudo-substrates exhibiting drastically reduced dislocation densities. These layers are fully strained and are able to support high temperature annealing (similar to 1060 degrees C needed for the subsequent CMOS fabrication step) without any relaxation. The resulting ultra-thin, defect-free, and fully strained SiGe layers exhibit high Ge content and superior optoelectronic quality, opening new opportunities for the integration of advanced SiGe channels in next-generation FD-SOI technology.

We demonstrate that novel ultra-thin silicon-germanium-on-insulator (UT-SGOI) templates, fabricated by an optimized Ge thermal-condensation process, can serve as an alternative substrate to industrial Smart-CutTM UTSOI wafers for the epitaxial growth of thick LPCVD SiGe epilayers (approximate to 840 nm, similar to 42% Ge). Direct comparison with nominally identical SiGe layers grown on UT-SOI reference wafers reveals a clear advantage of the condensed UT-SGOI templates. Capacitance-voltage, conductance, and impedance analyses show strongly suppressed lowfrequency dispersion and a reduced defect-related contribution in the SiGe/UT-SGOI stacks, consistent with a lower density of electrically active traps and more stable, device-grade behavior. These electrical improvements correlate with the excellent structural quality of the epilayers, evidenced by atomically sharp interfaces and the absence of threading dislocations. Overall, Ge-condensed UT-SGOI emerges as a reliable, CMOS-compatible template for high-performance SiGe epitaxy, providing a practical pathway toward advanced electronic and silicon-photonics platforms.

Sustainable avalanche operation was demonstrated and investigated on lateral E-mode GaN HEMT devices with sub-micrometer gate length. Through an extensive analysis: a) we demonstrated that sustainable avalanche operation is made possible by the presence of a subthreshold drain-source leakage, that initiates impact ionization; b) this process clamps the drain voltage to values lower than the dielectric breakdown voltage, thus preventing the catastrophic failure of the devices; c) avalanche operation is sustainable, and the related voltage strongly depends on the device geometry; d) spectrally resolved electroluminescence measurements demonstrate the presence of band-to-band luminescence, ascribed to recombination of holes, generated by impact ionization during the process. Finally, e) the positive temperature coefficient of avalanche voltage has been demonstrated. Support to the interpretation was obtained based on TCAD simulations.