意法半导体

The crystallization of initially amorphous Ge-rich Ge-Sb-Te nanostructures is investigated using fast thermal pulse heating, coupled with in situ scanning transmission electron microscope-energy dispersive spectroscopy (STEM-EDX) and high resolution (HR)-Transmission electron microscopy (TEM) analyses. Chemical analysis reveals a Te-Ge interdiffusion mechanism occurring at the bottom interface between the Ge-rich GST (GGST) layer and the underlayer (UL). The initially Ge-rich cell shows increasing Te-enrichment as the temperature increases. The onset of crystallization was found to start at 350 degrees C with pure cubic Ge grains appearing first, followed by cubic GST at 390 degrees C. Initially localized at the interfaces, the crystallization of both phases spreads heterogeneously throughout the cell. The spatial distribution of grains is compared with the variations in chemical composition at the nanometric scale.

Sustainable avalanche operation was demonstrated and investigated on lateral E-mode GaN HEMT devices with sub-micrometer gate length. Through an extensive analysis: a) we demonstrated that sustainable avalanche operation is made possible by the presence of a subthreshold drain-source leakage, that initiates impact ionization; b) this process clamps the drain voltage to values lower than the dielectric breakdown voltage, thus preventing the catastrophic failure of the devices; c) avalanche operation is sustainable, and the related voltage strongly depends on the device geometry; d) spectrally resolved electroluminescence measurements demonstrate the presence of band-to-band luminescence, ascribed to recombination of holes, generated by impact ionization during the process. Finally, e) the positive temperature coefficient of avalanche voltage has been demonstrated. Support to the interpretation was obtained based on TCAD simulations.

We demonstrate that novel ultra-thin silicon-germanium-on-insulator (UT-SGOI) templates, fabricated by an optimized Ge thermal-condensation process, can serve as an alternative substrate to industrial Smart-CutTM UTSOI wafers for the epitaxial growth of thick LPCVD SiGe epilayers (approximate to 840 nm, similar to 42% Ge). Direct comparison with nominally identical SiGe layers grown on UT-SOI reference wafers reveals a clear advantage of the condensed UT-SGOI templates. Capacitance-voltage, conductance, and impedance analyses show strongly suppressed lowfrequency dispersion and a reduced defect-related contribution in the SiGe/UT-SGOI stacks, consistent with a lower density of electrically active traps and more stable, device-grade behavior. These electrical improvements correlate with the excellent structural quality of the epilayers, evidenced by atomically sharp interfaces and the absence of threading dislocations. Overall, Ge-condensed UT-SGOI emerges as a reliable, CMOS-compatible template for high-performance SiGe epitaxy, providing a practical pathway toward advanced electronic and silicon-photonics platforms.

In recent years, the demand for deploying machine learning models on edge devices has surged, requiring the evolution and deployment of energy efficient and tiny neural network topologies. This paper presents a lightweight neural architecture search framework designed to identify convolutional neural networks specifically deployable in the very scarce assets of the Intelligent Sensor Processing Units (ISPUs), a single package integrating accelerometer and gyroscope sensing and low energy programmable processor. The framework runs both training and inference on a multiprocessor edge device, such that the models are lightweight and computationally efficient to operate within the 40 KiB embedded memory limit of the ISPUs. The framework utilizes a derivative-free search strategy, inspired by Occam’s razor to explore the architectural design space effectively, balancing model size, accuracy, and computational complexity. Models were generated for the PAMAP2 and SHL datasets to perform human activity recognition. For each dataset, a separate model was generated for every user and for each device carry position. Experimental results demonstrate that the proposed workflow successfully and automatically devises topologies that meet the stringent memory requirements of the ISPU. It also provides competitive performance in terms of accuracy and speed. This work contributes to the field of edge computing by enabling the embedded-on-premises operations, therefore enhancing the autonomy and privacy of personalized intelligent devices.

In this work, a novel understanding of the main failure mechanism of a Schottky p-GaN gate AlGaN/GaN HEMT subject to forward gate stress is reported. First an experimental characterization of the gate leakage current (IGSS) at different temperatures is reported. Then, Technology Computer Aided Design (TCAD) simulations are used to reproduce the experimental IGSS thanks to the impact ionization model, also at different temperatures. Simulation results underline how the stressed regions for the Device Under Test (DUT) at high gate biases are the Schottky/p-GaN interface, the p-GaN/AlGaN barrier interface, and p-GaN sidewalls. Moreover, Time Dependent Gate Breakdown (TDGB) measurements were done, and the TEM analysis on the failed device showed the lattice crystal damage located at the p-GaN/AlGaN interface, in accordance with TCAD simulations' current density distribution at high voltage gate stress.