Memristor-Aided Logic (MAGIC)-based In-Memory Computing (IMC) executes Boolean operations directly within crossbar arrays, addressing the von Neumann bottleneck. However, the efficiency of MAGIC-based arithmetic circuits strongly depends on mapping strategies. This work presents a unified, parallel row-wise, multi-scheduling-aware framework for efficient crossbar mapping of MAGIC-based adders, multipliers, and dividers. The proposed design flow integrates automated Register-Transfer Level (RTL) generation, NOT/NOR-constrained logic synthesis, and multiple scheduling strategies, namely As Soon As Possible (ASAP), As Late As Possible (ALAP), and Resource-Constrained (RC), to systematically extract micro-operations and evaluate latency, memristor counts, crossbar size, and energy. Comprehensive benchmarking across multiple arithmetic architectures (8–64-bit adders/multipliers and up to 128/64-bit division) demonstrates that RC scheduling consistently reduces crossbar size without increasing logic depth. Among the evaluated designs, Brent–Kung (BK) adders and Dadda Tree (DT) multipliers provide the best scalability, while Restoring Array Dividers offer high efficiency. The proposed mapping framework achieves reduced latency and improved area–latency trade-offs compared to prior MAGIC designs, and comparative evaluation shows competitive performance for adders and substantially lower latency with improved scalability for multiplier architectures compared with representative MAC-, MAJ-, and AIG-based IMC implementations.
Rust is a modern systems level language with built in safety features providing strong guarantees to memory safety and defined behavior. In this work we identify challenges and opportunities for adopting Rust in the context of safety-critical systems. In particular we focus on software safety and security requirements akin to ISO 26262, IEC 61508, and ISO/SAE 21434. We discuss Rust based development in relation to commonplace C/C++ software design and validation processes. Furthermore we compare two distinct system categories: hosted and bare-metal systems and which opportunities and challenges developers face in the context of safety and security certification in each of them.
Decentralized biometric authentication systems must balance recognition accuracy, computational efficiency, security, and scalability while ensuring data integrity and robust identity lifecycle management. This paper proposes a blockchain-anchored decentralized biometric authentication framework integrating deep facial embedding extraction, seed-based cancelable transformation, Sparse Representation–based Classification (SRC), encrypted template protection, and decentralized storage. A pretrained ArcFace model generates 512-dimensional facial embeddings, which are transformed into cancelable representations using a deterministic seed derived from SHA-256 hashing of preprocessed enrollment images, ensuring non-invertibility, revocability, and unlinkability without storing transformation parameters. The transformed embeddings are reduced to 128 dimensions using Principal Component Analysis (PCA), achieving approximately 75
When executing common Neural Networks (NNs) on custom AI accelerators, the high performance suggested by advertised Giga or Tera Operations per Second (GOPS/TOPS) is typically not achieved, as low hardware utilization often leads to an effective performance in the single-digit percentage range of the theoretical peak. This discrepancy arises as NNs are typically designed without accounting for the target hardware, leading to inefficient mappings and software optimizations that fail to deliver the expected gains. Addressing this, we present a hardware-aware workflow that combines accurate latency modeling and design space exploration to optimize both neural network architectures and the underlying systolic-array-based accelerator. We develop and validate two high-precision latency models for two different Row-Stationary (RS) dataflows on our target accelerator. Using these models together with a structured search space generation, we generate Pareto-optimal search spaces in terms of achieved GOPS and latency for a given hardware target, and use these for a Bayesian Bayesian Hardware-Aware Neural Architecture Search. We further explore the accelerator design itself in a subsequent hardware DSE stage, varying the PE array dimensions and clock ratio to identify hardware configurations that maximize efficiency and minimize inference latency for each network and dataflow. We demonstrate our approach on ResNet-like networks. On the original hardware, the discovered ResNet-50-like architecture achieves an 85
Space-based Automatic Dependent Surveillance-Broadcast (ADS-B) can provide seamless real-time surveillance service for global aircraft due to its global coverage characteristic compared with terrestrial ADS-B systems. However, the low signal-to-noise ratio (SNR) caused by long transmission distance degrades the continuity in the required surveillance performance (RSP). To ensure surveillance continuity, this paper proposes a coherent reception method based on the expectation maximization (EM) algorithm, realizing high-sensitivity reception for space-based ADS-B signals with low SNR. The reception requirements and the SNR threshold when using the coherent method are first analyzed. An EM model is then established to estimate ADS-B signals’ carrier frequency offset (CFO) and carrier phase offset (CPO) accurately. Simulation experiments and in-orbit test results show that the reception sensitivity metric of space-based ADS-B receivers can be effectively heightened through the proposed method, which can reach -102 dBm at 90
Network intrusion detection faces significant challenges from high-dimensional noisy traffic data, ambiguous class boundaries, and insufficient modeling of inter-sample relationships. To address these issues, this paper proposes GIC-IDS, a unified intrusion detection framework that integrates graph structure learning, information bottleneck, and contrastive learning. Specifically, a traffic graph is constructed to capture similarity relationships among traffic samples, and a graph neural network is employed to learn structure-aware representations. An information bottleneck module is then introduced to suppress redundant information and noise, while contrastive learning further improves intra-class compactness and inter-class separability. Experimental results on the UNSW-NB15 and CIC-IDS2017 demonstrate that the proposed method consistently outperforms representative baseline methods in terms of detection accuracy, robustness, and generalization capability.
Data elements, the core assets fueling AI and big data, face an inherent conflict between circulation utility and privacy preservation. While blockchain and Zero-Knowledge Proofs (ZKPs) provide a decentralized foundation for trust, existing systems suffer from prohibitive computational overhead when handling large-scale datasets. To address these bottlenecks, a novel entropy-driven probabilistic ZKP-based auditing framework, termed Block-Sampling, is proposed for efficient and secure data circulation. The framework leverages a control-data separation architecture, utilizing high-performance public blockchains as an immutable ledger for data commitments and a decentralized entropy source for generating unpredictable sampling indices. Unlike traditional systems, the ZKP construction and verification are conducted off-chain by a regulatory authority or data consumer, which asynchronously validates the sampling proofs against on-chain random seeds. This decoupling effectively neutralizes sampling bias while bypassing blockchain’s execution limits. Experimental evaluations indicate that the proposed framework achieves a 20x reduction in total computational workload, maintaining a per-sample proving latency of approximately 2s even for massive datasets with 10^6 records. With a commitment-to-challenge latency maintained at ∼ 1 s on the Sui blockchain, Block-Sampling significantly outperforms prior methods in balancing security with industrial-scale throughput.
Sampling clock duty cycle error degrades the performance of downconverting dual-edge sampling systems, requiring correction circuitry to guarantee the optimal duty cycle at the sampling location. This paper derives the theoretical effect of duty cycle errors in such systems and studies the technique of averaging samples to mitigate the problems. The analysis concludes that such a system can be designed in a manner where the duty cycle error causes no non-linearity, and only gain and phase errors. However, even these may result in non-linearity in time-interleaved systems, requiring duty cycle correction. An automatic duty cycle corrector used in a dual-edge downconverting sampling system is demonstrated in this paper. The proposed tuning circuit controls the DC level of the reference clock signal according to the detected duty cycle. The proposed duty cycle detector has automated self-calibration to ensure robustness under process, voltage and temperature variations. The corrector is designed to be used with sampling clock frequencies up to 12 GHz, which results in 24 GS/s in dual-edge sampling. The operation of the corrector is verified in system simulations that demonstrate its capability to reduce the effects of incorrect duty cycle over a wide frequency range of 2–12 GHz. In the simulations, the duty cycle tuner achieves 16–74
To address the need for lightweight and low-latency protection in massive resource-constrained 5G Internet of Things (IoT) systems, this paper proposes Key-Controlled Modulation Hopping and Constellation Rotation (KMHCR). KMHCR is designed as a physical-layer confidentiality-enhancement mechanism that avoids bit-wise full-payload encryption in the protection pipeline. It uses a shared key derived from channel-reciprocity secret key generation to drive a stateless, counter-based pseudo-random function, which determines a 5G-compliant modulation scheme and a quantized constellation rotation angle for each packet without requiring fragile per-packet state synchronization. For legitimate users, these operations introduce only lightweight signal-domain processing, whereas an unauthorized receiver must jointly infer the modulation type and the phase rotation from the observed signal. To evaluate the robustness of the proposed mechanism against intelligent attacks, we construct a 3GPP-compliant 5G adversarial dataset covering six modulation types, multiple signal-to-noise ratio regimes, and realistic channel impairments. Experimental results with multiple state-of-the-art deep learning-based AMC models show that KMHCR can substantially reduce the recoverable throughput of unauthorized receivers under the considered adversarial setting. These results support the use of KMHCR as a lightweight complementary protection mechanism for 5G IoT communications.
The unprecedented growth of big data in modern networked infrastructures has intensified the complexity of cyberattacks, making intrusion detection increasingly challenging in heterogeneous, high-volume, and rapidly evolving environments. Traditional intrusion detection systems (IDS) often suffer from scalability limitations, rigid rule-based structures, and high false-positive rates, which restrict their adaptability to emerging threats and zero-day exploits. Recent advancements in Artificial Intelligence (AI) offer promising capabilities for automated intrusion detection; however, the performance of these models remains highly sensitive to optimal architectural and hyperparameter configurations. To address these gaps, this study proposes a scalable and context-aware hybrid IDS framework that integrates a Long Short-Range Transformer (LSRT) for hierarchical sequential modeling with a Deep Gradient Boosting Classifier (DGBC) for structured traffic analysis. The entire pipeline is optimized using the Tree-Structured Parzen Estimator (TPE), a state-of-the-art probabilistic optimization method known for efficient exploration of complex hyperparameter spaces and superior performance in large-scale learning systems. The proposed LSRT–DGBC–TPE framework is comprehensively evaluated across six benchmark intrusion detection datasets—CICIDS2017, CICIDS2018, UNSW-NB15, BoT-IoT, NSL-KDD, and TON_IoT—covering a wide spectrum of modern cyberattack vectors, including DDoS, botnet, brute force, reconnaissance, infiltration, system compromise, and IoT-centric anomalies. The proposed LSRT–DGBC–TPE hybrid IDS achieved a maximum cross-dataset accuracy of 99.18
Currently, there are very few corpora available online for dysarthric speech. Collecting large amounts of dysarthric speech data poses significant challenges, including locating individuals with dysarthria and recording their speech in a suitable setting. To address the issue of data scarcity, this paper proposes fusion of different data augmentation techniques: speaking-rate modification, pitch modification, formant modification, and vocal-tract length perturbation (VTLP). Our baseline setup employs an artificial neural network (ANN) model with mel-frequency cepstral coefficients (MFCC) features. A suitable feature set was identified through feature-based analysis in a speaker-dependent manner to enhance the baseline. Subsequently, each of the four augmentation methods was explored by varying their respective modification factors to find the optimal modification factor for each method individually. Following this, combinations of augmentation techniques were examined to determine the best augmentation strategy. Later, the study was extended for the speaker-independent settings as well. The findings indicate that augmentation can significantly aid in the severity classification of dysarthria, especially addressing the data scarcity issue. Furthermore, the classification performance improves with the proposed fusion of multiple different augmentation techniques. With the proposed data augmentation fusion methods, relative improvements of 42.86
This paper presents a hardware-aware bit-allocation framework for pre-trained 2D and 3D CNNs to simplify volumetric data processing. The proposed scheme explores tradeoffs between prediction accuracy and hardware limitations by forming a multi-objective optimization problem that is solved using a modified Particle Swarm Optimization (PSO) algorithm. Efficient convergence of the proposed algorithm produces a set of optimized word-lengths for weights and activations for each layer of CNNs that is conducive to an efficient hardware design. The proposed bit-allocation framework satisfies three conflicting objectives of latency, resource utilization, and inference error. The selection of the final word-lengths is from a Pareto-optimal set which is based on given preferred parameters for the target CNN models. The quantization framework has been evaluated for three modern 3D CNNs, I3D, C3D and R(2+1)D. Experimental results have shown a 48
In this paper, a 16-nm 1P9M FinFET technology is used to design a computing-in-memory architecture based on a 4-kb single-ended SRAM. The proposed 6T SRAM cell enables an energy-efficient architecture by eliminating the direct connection between the complementary bit line (BLB) and the storage node Q. An Ultra-low threshold voltage (ULVT) transistors in the 2T switch reduce the requirements for capacitors and current compensation circuitry. Additionally, ULVT transistors are integrated into the control circuits of both the SRAM core array and the CIM core, reducing delay caused by threshold voltage drops in the ultra-low supply voltage environment of the 16-nm technology node. The resulting architecture efficiently supports the core operations for convolutional neural networks (CNNs), including addition, signed multiplication, and logical functions. This work highlights the potential of SRAM-based CIM architectures that deliver an energy efficiency of 75.47 TOPS/W and an area efficiency of 140.25 GOPS/mm2 at a maximum operating frequency of 500 MHz.
In the current era, healthcare is precious for all, so recent technology helps monitor the patient’s health via sensors and nodes, collect the same data, and analyze the patient’s condition. This is a technology known as a wireless body area network (WBAN). Nano-sensor devices are attached to the human body as part of WBAN to collect and monitor patient data, but have limited processing power and battery life. So, it cannot perform heavy computations within the node. Edge computing addresses this issue by processing data and reducing response times (in a near-edge node), which also helps mitigate delays and offloads work from WBAN nodes, but creates a privacy risk. Sensitive patient health information can be exposed through cyberattacks, unauthorized access, or profiling from edge nodes. This research proposes that PrivEdge-WBAN (Privacy-Preserving Edge Computing for WBANs) is integrated with edge computing, creates a framework for authentication and secure data processing, and supports new privacy-preserving and energy-efficient techniques. The proposed model combines lightweight Homomorphic Encryption (HE) and Differential Privacy (DP) to enable privacy-preserving computations and security at the edge node while maintaining energy efficiency. Moreover, the proposed framework combines an adaptive security engine that dynamically regulates cryptographic processes and authentication complexity derived from real-time energy levels and device workload. PrivEdge-WBAN aims to provide a comprehensive solution for security, privacy, and battery conservation in the real-world applications of WBAN. The outcome of this research can significantly influence the design of sustainable and secure surveillance systems for the healthcare sector, particularly for chronic illnesses, aging care, and other emergencies.
Securing medical images during transmission is a challenge in this cyber world due to the patient data privacies’ and the limitations of conventional encryption and compression techniques, which often compromise either security or efficiency. To address this issue, a dual-framework approach that integrates Generative Adversarial Networks (GANs) for encryption with an Enhanced Super Resolution Network (ESRNet) for reconstruction has been proposed in this work. The medical images are divided into 3 ⋅ 3 segments, encrypted using a random sequence generator based on Henon and Tent maps, and downsampled to one-fourth of their original resolution for efficient transmission, while ESRNet at the receiver end reconstructs the high-resolution image. The experimental results demonstrate the robustness of this framework, achieving significant performance, along with a minimum of 26.7
State-of-the-art automatic speech recognition (ASR) systems often struggle to maintain reliability and security in noisy or unpredictable environments, especially when trained on limited data. Bayesian approaches introduce uncertainty modeling to address this challenge. However, existing methods often apply a uniform uncertainty modeling strategy across all noise conditions, which may limit performance. In this work, we propose a secure end-to-end reparameterized Bayesian long short-term memory (LSTM)-ASR framework that captures epistemic (model) and aleatoric (data) uncertainties by modeling network weights and Mel-frequency cepstral coefficients (MFCCs) as Gaussian distributions, respectively. We evaluate the proposed framework on the AudioMNIST and Google’s Speech Commands datasets in the presence of real-world noises collected from the Microsoft Scalable Noisy Speech Dataset (MS-SNSD). Our findings indicate that epistemic uncertainty is more effective for stationary background noises, such as air conditioning and traffic, while aleatoric uncertainty is superior for transient and unpredictable noises, including keyboard typing and neighboring speech. These results show how important it is to choose the right uncertainty modeling method based on the type of noise to make ASR systems more secure and reliable in noisy settings.
This paper proposes an adaptive graph recursive least M-estimate (GRLM) algorithm for graph signal processing, aimed at estimating graph signals in the presence of impulsive noise. The algorithm employs a robust M-estimator as its objective function, effectively mitigating the adverse effects of large estimation errors caused by impulsive noise. Compared to the recently proposed adaptive graph least mean pth power (GLMP) algorithm, the GRLM algorithm converges to a stable graph signal with fewer iterations. Unlike the adaptive graph normalized least mean squares (GNLMS) algorithm, the GRLM can accurately reconstruct graph signals corrupted by impulsive noise with heavy-tailed characteristics. To further improve the performance of GRLM, we propose a variable forgetting factor GRLM (VFF-GRLM) algorithm. Simulation results demonstrate that the GRLM algorithm shows superior robustness compared to both the GNLMS and GLMP algorithms, and the performance of the improved VFF-GRLM algorithm is further enhanced.
The advancement of machine learning (ML) has made autonomous vehicles (AVs) viable, offering benefits in user comfort and traffic efficiency. However, AV safety depends on the performance and reliability of these ML models, which can be compromised by adversarial attacks. In traffic sign classification, such attacks can be carried out by placing crafted stickers on road signs to mislead ML-based image classifiers. This work proposes a hybrid defence system for traffic sign classification under sticker attacks, specifically targeting resource-constrained devices. The system integrates an adversarial detector (AD) subnetwork with the main classifier to detect potential attacks. Upon detection, it relies on auxiliary models constructed using domain knowledge and enhanced with the Defense against Occlusion Attack (DOA) technique. Designed for deployment on low-cost FPGAs, the system uses Binarised Neural Networks (BNNs) for efficient hardware implementation. It achieves 93.82 ∼ 2.8 W power consumption, or up to 32
Image encryption protects sensitive information against malicious attacks in various applications, including the Internet of Things (IoT). However, lower computational complexity compromises the security in image encryption. Computationally intensive encryption algorithms make the system unreliable for real-time scenarios. This research work fuses machine learning and encryption algorithm. In the proposed work, blocks are constructed from an image, and for each block, features such as entropy, energy, contrast, and homogeneity are utilized to train the classifier to classify the block as sparse, intermediate, or dense. Sparse block containing less information and is encrypted with Gray codes, whereas, the intermediate and dense blocks holding more information are encrypted using advanced encryption standard (AES) to reduce processing time. In addition, the hardware-optimized proposed hybrid image encryption framework further decreases the computational time required for image encryption. The proposed AES hardware implementation enhances both throughput and area efficiency through composite field arithmetic (CFA) in GF((2^4)^2) , facilitating a combined encryption and decryption architecture. Optimized arithmetic operations reduce hardware utilization. The pipelined key expansion and SubByte architecture enhance the computation time. The proposed design is implemented on Virtex-6 XC6VLX240T for AES-128 and utilizes less hardware than existing techniques while achieving 5.14 Gbps throughput. The proposed hybrid image encryption framework encrypts a 512× 512 grayscale image with rich in information within 22.35ms with optimal security.
We consider deep learning-based perception in real-time, safety-critical cyber-physical systems (CPS), such as autonomous driving and robotics, where embedded computing platforms typically operate under limited hardware resources due to SWaP-C (Size, Weight, Power, and Cost) constraints. In computer vision-based deep learning perception, adversarial patch attacks have emerged as a powerful method for deceiving classifiers. These attacks involve placing a carefully crafted patch on the input image, constituting a physically realizable and practical threat. Defense techniques against such attacks remain an active area of research. In this study, we evaluate and compare six well-known certifiable adversarial patch defenses, encompassing 14 models, across three different hardware platforms. We analyze their performance in terms of accuracy and processing time, highlighting key trade-offs. This paper aims to serve as a reference for selecting adversarial patch defense algorithms in real-time, safety-critical applications.
