Given that most CS students, especially at liberal arts colleges, lack engineering or logic design experience, we employ visualization in our computer architecture course to expedite student learning. By having students design and learn visually, students developed a deeper understanding and appreciation of computer architecture. Within a single semester, the course equips students with the skills to engage in innovative computer architecture research. We describe the course materials, student projects, and undergraduate research. By combining visualization with experiential learning, we broaden participation and encourage undergraduate research in computer architecture. The course materials will be made publicly available.
A new tool called Visceral VCD was utilized to replace FPGA hardware during the pandemic. Its functionality was proven utilizing multiple projects in a digital logic course. The pedagogy of the assignments is discussed in detail, as well as how the use of Visceral VCD allowed electrical and computer engineering students to complete all coursework remotely during quarantine. Use of this tool was continued after quarantine restrictions eased due to its effectiveness. Visceral VCD can be used in place of hardware for multiple hardware description languages and FPGA development environments.
Computer architecture students today arguably do not have as close a connection to energy as they do to performance. Specifically, they are not trained to reason about energy in a quantifiable way. Architecture students are taught that performance and energy are considered equally important. However, most course material focuses on a performance-driven narrative, meaning that students learn about processors, memories, networks, and systems with a strong sense of the performance implications, but with little intuition for the energy implications. On the other hand, VLSI students concretely learn about energy, but they are immersed in a world of gates and transistors and do not connect their understanding about energy back up to the abstraction of SoC-level components. How can we bridge this gap to enable architecture students to reason about the energy implications of hardware design concepts, directly within a computer architecture class? In this work, we attempt to mitigate these challenges by introducing a teaching methodology that integrates energy into pipeline diagrams. We include examples of specific classroom tools including the representation of an energy map, and we show how pipeline diagrams augmented with an energy map can enable first-order quantitative comparisons of performance, energy, and power across different design points. The approach is simple enough for lecture, in-class activities, and in exams. We hope this approach can train future students in thinking from first principles in evaluating performance-energy tradeoffs.
Computer architecture is primarily studied through simulation. Most existing simulators are either comprehensive research tools, or ones targeting a single area within computer architecture. CADSS is an open source computer architecture simulator that can support simulations written in multiple languages across a variety of areas of computer architecture, either individually or combined together. It is designed to support student learning, as well as assessment by instructors.
This paper describes the computer architecture content in Dive into Systems, our free, online textbook that introduces a broad range of computer systems topics. Dive into Systems assumes only a CS1 background of the reader, and includes numerous examples and illustrations to foster a reader’s understanding of its content. Our textbook is designed to be used as a primary textbook for a range of courses that introduce computer systems and computer architecture topics. It also serves as a supplementary text in upper-level undergraduate and graduate level courses to provide background material on computer architecture, systems, and parallel computing. In addition to presenting the details about our book’s coverage of computer architecture topics, we also discuss the overarching themes of our textbook and our motivations for writing a free online textbook to introduce computer systems topics. Our book is currently used by more than 45 institutions in a wide range of courses, including undergraduate computer architecture courses.
Scientists, engineers, and researchers leverage high-performance computing (HPC) systems to perform complex computations and process large amounts of data. Designing, developing, and operating HPC systems have a steep learning curve, thus making it crucial to train a highly skilled and knowledgeable workforce in order to keep up with the rapidly evolving field, drive innovation, and meet the increasing demand for HPC across various sectors. Limited access to HPC educational resources is the main deterrent to training HPC talent. This paper addresses two primary culprits for the limited access: the high cost of production systems and the lack of realistic full-stack HPC training. Cutting-edge hardware is usually expensive and requires specialized facilities. Moreover, large HPC facilities typically discourage experimenting with the systems since they run production computation workloads and require minimal disturbance. Furthermore, HPC training often does not reflect the scale or complexity of production systems. This lack of realistic training support makes education in this area particularly difficult and ineffective. This paper proposes an educational framework for HPC that includes the development of a low-cost and flexible platform design for users in diverse fields. It allows study and experimentation with multiple realistic elements involved in a production HPC ecosystem. DEMAC, the Delaware Modular Assembly Cluster, is a set of 3D-printable frames designed to house embedded systems and auxiliary systems in a way that emulates HPC platforms. The teaching framework focuses on practical training as an education model in which learners reinforce theoretical knowledge with hands-on experience. If successful, this effort will contribute fundamentally to scientific research, technological advancements, HPC workforce development, and economic growth.
The traditional model of assigning textbook problems for homework is endangered by the ability of students to find answers to almost any published problem on the web. An alternative is a dual-submission approach, where students submit their work, then receive the solutions, and submit a second metacognitive reflection, explaining any errors they made. Students’ scores can depend on the quality of their second submissions alone or the combined quality of their first and second submissions. We tried this approach in a class on parallel computer architecture. We report students’ personal experience based on their questionnaires responses. In addition, we quantitatively compare students’ performance on test questions related to dual-submission homework against their performance on other questions and previous semesters’ student performance on similar questions. Students overwhelmingly preferred this approach and thought they learned more from it, but evidence about whether it improved their learning was inconclusive. We also analyze the continued viability of this approach in the era of large language models.
The COVID-19 pandemic necessitated courses being moved online and preferably made asynchronous. This was particularly challenging for small liberal arts colleges, whose faculty and students are used to close interaction. This paper describes the set of interactive asynchronous mini-lectures and online lab assignments used for an undergraduate computer architecture course at Mills College. The materials, which follow best practices for active learning, are available online for faculty at other institutions to use and modify under a Creative Commons license. We also discuss the pros and cons of making the course self-paced.CCS CONCEPTS• Applied computing → E-learning; Interactive learning environments; • Social and professional topics → Computer science education.ACM Reference Format:Ellen Spertus. 2021. Interactive Asynchronous Online Computer Architecture Education. In Proceedings of Workshop on Computer Architecture Education 2021 (WCAE ’21). ACM, New York, NY, USA, 8 pages. https: //doi.org/10.1145/nnnnnnn.nnnnnnn
It is the golden age of practical computer architecture. The rise of open source hardware designs and the open RISC-V instruction set architecture enables us to build courses around real processor cores of varying complexity. While it is desirable to build lab assignments and projects around actual processors, the common presentation of hardware designs in the form of waveforms is not very accessible to students, especially outside of EE. In this paper I present an open source framework for microarchitectural traces along with a simple but efficient visualization tool called pipeline-viewer. It is targeted at computer architecture classes where microarchitecture details are taught and real world demonstration is helpful.ACM Reference Format:Stefan Wallentowitz. 2021. A Framework for Microarchitecture Traces as Abstraction Layer in Computer Architecture Education. In Proceedings of WCAE 2021: Workshop on Computer Architecture Education (WCAE 2021). ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/nnnnnnn.nnnnnnn
We describe our experience teaching an undergraduate capstone (and elective graduate course) in computer architecture with a semester-long project in which teams of five students design and implement an out-of-order (OoO) pipelined processor core using the open-source RISC-V instruction set. The course content includes OoO scheduling algorithms for instructions to exploit instruction-level parallelism (ILP), example designs, caching, prefetching, and virtual memory. The labs and projects help students gain proficiency with the SystemVerilog language.Students use the concepts learned in class to design processors with the goals of achieving correctness and high performance for a suite of representative test programs. Using RISC-V enables students to validate and benchmark their designs by compiling test programs using GCC with a custom linker. By collaborating as a team, students learn how to write and debug a large code base over the two-month project.For computer architecture educators, we describe technical aspects of the final project and common advanced features implemented by students. We hope describing our experience serves not only to demonstrate a method of teaching modern computer architecture, but also to inspire other course designs centered around other aspects of modern computer architecture (GPUs, FPGAs, hardware/software codesign, etc). We have open-sourced our lab and project materials to enable others to teach similar courses.CCS CONCEPTS• Social and professional topics → Computer engineering education.ACM Reference Format:Stephen A. Zekany, Jielun Tan, James A. Connolly, and Ronald G. Dreslinski. 2021. Teaching Out-of-Order Processor Design with the RISC-V ISA. In ISCA Workshop on Computer Architecture Education (WCAE ’21), June 17, 2021, Virtual Event, USA. ACM, New York, NY, USA, 8 pages. https://doi.org/10.1145/nnnnnnn.nnnnnnn
Ripes is a visual computer architecture simulator built around the RISC-V ISA. The main feature of Ripes is its tight integration of a built-in assembler, compiler support, and cache simulator, all centered around a visual microarchitecture simulator. Several microarchitectural models are provided to explore the evolutions of a typical processor pipeline, such as the different iterations of processors when going from a single-cycle model to a classic RISC five-stage pipeline. This paper details the core features of Ripes, the design decisions behind them, as well as thoughts on how Ripes may fit into a larger ecosystem by joining the growing movement around open hardware toolchains. Ripes is an actively maintained open-source project and is at the time of writing used in teaching at various universities, as well as in nonacademic settings.ACM Reference Format:Morten B. Petersen. 2021. Ripes: A Visual Computer Architecture Simulator. In Proceedings of WCAE ’21: IEEE Workshop on Computer Architecture Education (WCAE ’21). ACM, New York, NY, USA, 8 pages.
LupIO is a comprehensive and open-source collection of education-friendly I/O devices. This collection defines the interfaces of the most common devices found in modern RISC-based computers, and makes it possible to build complete systems using only LupIO devices, even complex multicore systems. Each device interface is designed to be simple and clear, with an optimal balance between features and complexity. The register maps exposed by the devices are neatly organized by type and arranged consistently across devices. Developing implementations of LupIO devices, as well as corresponding device drivers, is meant to be straightforward and accessible to students at the undergraduate and graduate level. As a proof of concept, LupIO was entirely implemented as virtual devices in QEMU, along with corresponding device drivers in Linux, and we were able to successfully boot a RISC-V based dual-core virtual machine. The specifications are available at https://gitlab.com/luplab/lupio. CCS CONCEPTS • Computer systems organization $\rightarrow$ Architectures; •Applied computing $\rightarrow$ Education. ACM Reference Format:Joël Porquet-Lupine. 2021. LupIO: a collection of education-friendly I/O devices. In Proceedings of Workshop on Computer Architecture Education (WCAE’21). ACM, New York, NY, USA, 8 pages. https://doi.org/10.1145/nnnnnnn.nnnnnnn
In this paper, we discuss how an embedded system course was transferred from classroom teaching to digital teaching using simulation tools instead of physical embedded systems hardware in a computer science undergraduate studies at the Bielefeld University of Applied Sciences. We aligned our teaching to RISC-V based hard- and software as we have seen advantages due to open source. Our approach is described and the evaluation of the course by our students is given and discussed.CCS CONCEPTS• Social and professional topics $\rightarrow$ Computing education;• Computer systems organization $\rightarrow$ Embedded systems.ACM Reference Format:Matthias Koenig and Robin Rasch. 2021. Digital Teaching an Embedded Systems Course by Using Simulators. In WCAE ’21: Workshop on Computer Architecture Education, June 71, 2021, Online. ACM, New York, NY, USA, 7 pages.
This paper describes the authors’ Digital Design and Computer Architecture: RISC-V Edition textbook. The book presents a unified 1-or 2-semester course on digital design and computer architecture. We have found that learning these topics together clarifies and solidifies understanding of both concepts. The textbook begins by describing digital design concepts and techniques, from number systems, logic gates, and transistor-level gate design to synchronous sequential circuits such as finite state machines and other common digital building blocks. It then builds on these concepts to teach computer architecture and processor design by introducing the RISC-V instruction set architecture (ISA), showing how to design three RISC-V processors with limited instructions, and describing various memory organizations, including caches and virtual memory. The textbook also describes logic design using hardware description languages (HDLs), covering SystemVerilog and VHDL side-by-side. The optional appendices and online chapters introduce the C programming language, embedded system design, and practical aspects of digital design including breadboarding, ASIC design, and transmission lines.CCS CONCEPTS • Architectures • Embedded Systems • Logic
Introductory-level computer architecture courses often rely on programs with a graphical user interface (such as Logisim) for processor design projects. While these tools provide an easy introduction into logic design, they can detach students from real-world design constraints such as ISA standard tests, and real-world ramifications such as timing and area. This paper introduces a testing flow based on open-source tools that allows Logisim-based designs to be built into ISA-test-compatible simulation binaries, synthesized into gate netlists, and compared for similarity. This flow was used in UC Berkeley’s fall 2020 Great Ideas of Computer Architecture course; out of 695 project submissions, over 96% achieved highly-functional designs as measured by the presented infrastructure. CCS CONCEPTS •Social and professional topics $\rightarrow$ Computer engineering education; •Computer systems organization $\rightarrow$ Reduced instruction set computing; Pipeline computing. ACM Reference Format: Ryan Lund, Connor McMahon, Dan Garcia, and Borivoje Nikolić. 2021. Improved Processor Design Project Testing. In Proceedings of WCAE ’21. ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/1122445.1122456
CSC 211: Computer Organization and Architecture at Grinnell College introduces computer science students to the basics of digital circuits, logic design, and computer organization/architecture. This course is designed to help students develop a deeper understanding of how processors function, and how their design can impact the code they write. During the course, students build components like adders, multiplexors, ALUs, and registers with real circuits, and larger components in a digital logic simulator (Logisim). This progression culminates in a four-week lab sequence where students create an assembler and datapath for the PIPS Instruction Set Architecture, which we have designed specifically for this course. In this paper we describe the design and specific learning goals of the PIPS architecture, the four-week lab sequence where students implement a working PIPS assembler and datapath, and our experiences using this lab sequence for the past three years. All student starter materials and instructions for these labs are available at DOI:11084/10426, with solutions and grading infrastructure available to instructors upon request. CCS CONCEPTS • Computer systems organization $\rightarrow$ Reduced instruction set computing; • Applied computing $\rightarrow$ Education.ACM Reference Format: Charlie Curtsinger and Jerod Weinman. 2021. PIPS: An Instruction Set Architecture for Teaching Computer Organization. In WCAE ’21: Workshop on Computer Architecture Education, June 17, 2021. ACM, New York, NY, USA, 8 pages. https://doi.org/11084/10437
In our computer organization course, Logisim-evolution has been used for: building on the digital logic design topics, describing instruction-set design choices, implementing a single-cycle datapath and control for an ARMv8-subset architecture in increasing complexity, and demonstrating input/output mechanisms in sufficient detail to recreate the physical bare-metal assembly programming exercises. In this paper, we describe the designs we created and how they are utilized in our computer organization course. The materials are available on GitHub (github.com/mkayaalp/computer-organization-logisim).CCS CONCEPTS• Social and professional topics $\rightarrow$ Computer engineering education; • Computer systems organization $\rightarrow$ Reduced instruction set computing.ACM Reference Format:Mehmet Kayaalp. 2021. Using Logisim-evolution for Teaching Datapath and Control. In Proceedings of WCAE ’21: Workshop on Computer Architecture Education (WCAE ’21). ACM, New York, NY, USA,8 pages. https://doi.org/10.1145/nnnnnnn.nnnnnnn
Mastery-based learning is an approach in which students are graded based on their demonstrated mastery of explicit learning outcomes rather than by being awarded points less directly connected to course goals. Instead of submitting an assignment only once, students can use feedback to improve their work to increase their learning and grades. We describe our approach to mastery-based grading in introductory computer organization/architecture courses at two different institutions. Specifically, we allowed students to retake tests of basic skills as many times as needed, which was facilitated by programmatically-generated questions. For course projects, students were expected to refine and resubmit projects until they demonstrated mastery by passing all of the provided automated tests. We share our materials and experiences, including the challenge of loosening deadlines to provide students time for continued work without enabling them to fall irretrievably behind.CCS CONCEPTS• Applied computing $\rightarrow$ Interactive learning environments; Computer-assisted instruction; • Social and professional topics $\rightarrow$ Computer science education; Student assessment; • Computer systems organization $\rightarrow$ Architectures. ACM Reference Format:Ellen Spertus and Zachary Kurmas. 2021. Mastery-Based Learning in Undergraduate Computer Architecture. In Proceedings of Workshop on Computer Architecture Education 2021 (WCAE ’21). ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/nnnnnnn.nnnnnnn
Academic mentoring programming is a powerful tool used for supporting, engaging, and retaining students in their fields of study. Researchers have long known the positive effects of academic mentoring, particularly for students from underrepresented and marginalized backgrounds. The computer architecture community currently hosts an assortment of mentoring programs geared toward women, underrepresented students, junior graduate students, and undergraduates alike.In this work, we describe the current state of mentoring opportunities for students in computer architecture. In addition to summarizing various mentoring programs (e.g., CWWMCA, YArch, and uArch), this work details the organization and feedback from two programs (MaSA and MaSS) that the authors currently run and organize. Based on feedback from these short-term mentoring programs, along with relevant mentoring research literature, we identify opportunities for developing more productive longer-term mentoring programming for the computer architecture community. Following mentoring literature, this work makes a strong case for offering both short-term and long-term mentoring programs in the future; in particular, mentoring literature show the need for time in forming mentoring relationships for mentees to receive the multifaceted benefits of mentoring.ACM Reference Format:Elba Garza, Gururaj Saileshwar, Udit Gupta, Tianyi Liu, Abdulrahman Mahmoud, Saugata Ghose, and Joel Emer. 2021. Mentoring Opportunities in Computer Architecture: Analyzing the Past to Develop the Future. In WCAE ’21: Workshop on Computer Architecture Education, June 17,2021, Online. ACM, New York, NY, USA, 9 pages. https://doi.org/10.1145/nnnnnnn.nnnnnnn
