This paper describes the theory and implementation of a novel system for hardware synthesis from requirement specifications expressed in a graphical specification language called Symbolic Timing Diagrams (STD). The system can be used together with an existing formal-verification environment for VHDL leading to a novel methodology based on the combination of synthesis and formal verification. We show the feasibility of the approach and experimental results obtained with the system on the well known example of an industrial production cell, where both FPGA and ASIC hardware implementations were successfully synthesized.
This paper deals with exploration of hardware/software design space. The analysis is illustrated using a design of robot arm controller. The controller makes use of an adaptive speed control in real-time. Several architectural solutions are discussed with regard to their performance and cost. The goal is to select the best solution that satisfies the real-time constraints and minimizes the cost.
This paper describes a system for designing and implementing controllers for structured data processing. A graphical input style describes the format of the data to be processed along with the necessary control actions. Advantages over FSM approaches include: (1) ease of design changes, (2) ease of debugging, and (3) a shorter design cycle.
The paper concerns low power design of synchronous FSM and power estimation regarding a given input sequence. A novel and practical approach for state assignment is suggested bp means of which the average rate of register switching is reduced. We achieved more realistic power estimates in comparison with the probabilistic approach. Experimental results demonstrate the effectiveness of the proposed approach.
This presentation provides an overview of the 1076.1 effort to extend the well established VHDL language to support the description and simulation of continuous and mixed continuous/discrete systems. It begins with a brief history of the effort. That is followed by an overview of the foundations: the design objectives, the base VHDL 1076 language, and the applicable mathematical theory. The body of the presentation describes the elements of the extended language. Each language element is described in the context of the 1076.1 language architecture and illustrated by a brief example. The presentation ends with selected examples illustrating the use of the language for analog and mixed-signal applications.
In this paper, we propose an approach for designing fuzzy controllers. To reduce design time, we employ two high-level design methods: VHDL and VHDL-based logic synthesis, and Statecharts with a VHDL backend for graphical design description. A fuzzifier and a defuzzifier parts of a fuzzy control system are captured in VHDL, as these parts perform complex arithmetical operations. A rule base of the controller is described in Statecharts, and then is translated into VHDL. A complete description of the system is assembled in VHDL, and is synthesized using VHDL-based logic synthesis. The efficiency of the generated hardware is explored for FPGA technology.
In this paper an approach for the optimization of digital synchronous designs is described. The optimization is done for smaller components which are the result of a partitioning process. The actual optimization is done on a graph which reflects the communication structure between the modules. Sequential don't care conditions are extracted and used for sequential optimization. As experimental results show, the robustness of the subsequent logic synthesis methods can be increased while achieving a significant gain in cost and power consumption. This is shown by applying the described methods to a set of benchmarks obtained from high-level synthesis.
This paper presents an approach far system level specification and hardware/software partitioning with VHDL. The implications of using VHDL as a specification language are discussed and a message passing mechanism is proposed for process interaction. We define the metric values for partitioning and develop a cost function that guides our heuristics towards performance optimization under hardware and software cost constraints. Experimental results are presented.
In this paper we present a new approach for the realization of a BDD package. This approach does not depend on recursive synthesis operations, i.e. the ternary If-Then-Else-operator (ITE), to perform manipulations of Boolean functions; instead our basic operation MORE is based on exchanges of neighbouring variables and existential quantification. It is capable of combining an arbitrary number of Boolean functions in parallel. We discuss the difference between MORE and ITE and give experimental results to show the advantages of our implementation approach with respect to size and runtime.
We have applied a mixed-signal simulator and AHDL to the top-down design of industrial ICs. We report the design process from the system-level down to gate/transistor-level modeling and simulation applied to a real circuit. We have verified the robustness and effectiveness of our approach which resulted in shorter design process cycles and higher rates of success.
For high quality VLSI products, exhibiting very low escape rates, defect-oriented testing becomes mandatory. The design activity is more and more supported by hardware description languages, like VHDL; hence, the testing activity needs to follow this trend. In this paper, a VHDL-based methodology for test preparation of digital ICs is proposed and a new set of tools for defect-oriented VHDL fault simulation are presented, using a commercial VHDL simulator. The proposed methodology is also shown to be effective in supporting realistic fault diagnosis. Simulation results for benchmark circuits are presented.
As the number and diversity of computer-aided VLSI design tools grows, there is an increasing interest in workflow management. In this paper we describe an enhancement to the task schema approach to workflow management that allows for the automatic generation of workflows. Such a capability can significantly enhance designer productivity. It has been implemented in the Dedal program.
We present a hardware synthesis system that accepts system-level specifications in both Verilog HDL and C. A synchronous semantics is assumed for both languages in order to guarantee a uniform underlying model. The rationale for mixed input specifications is to support hardware/software co-design by allowing the migration to hardware of system modules originally described in the C language. We discuss assumptions and limitations of the input description style, a high-level synthesis system, and the application of such a system to some design examples.
In this paper a new enumerative algorithm called TINA is introduced that generates slicing placements optimal in both area and overall net length. It is designed to automate the task of placement for analog circuits given a set of modules with multiple realizations, a corresponding net list, and neighborhood relations. TINA reduces the overall net length to nearly one-fifth compared to a net length unaware enumeration algorithm while using only 1.6% more area and twice the CPU-time. TINA is based on enhanced shape functions that are capable of carrying net length information. TINA can be used either as a fully automatic analog placement tool, or as an interactive tool for creating extremely dense placements from a loose placement provided by the designer to establish neighborhood relations. In the first case another tool, e.g. PLACEBO, is used to compute neighborhood relations TINA is able to handle all major analog constraints like clustering framing, fixed orientations, fixed realizations, and symmetries.
A refinement calculus for the specification of real-time systems and their refinement to a VHDL behavioural description is set out here. The specification format is a logical triple with the look of a Z or VDM schema. Choices from a short menu of refinement operations gradually convert an initial specification to VHDL code through a series of mixed mode intermediates. The calculus is complete in the sense that if there is a code of the VHDL subset considered here (unit-delay waits and signal assignments but no delta delays) satisfying the specification, then it can be obtained by applying some sequence of the refinement operations. The result is "correct by construction".
We investigate the impacts of miniaturization of device dimensions that causes a paradigm shift in LSI design methodology. Major design issues in deep sub micron LSIs, namely, wire delay, circuit complexity and power consumption are discussed based on scaling theory. To resolve these issues, a concept called layout driven synthesis and optimization Is introduced. Based on this concept, EDA programs including circuit optimizer, clock tree synthesis, technology mappers and so on, have been developed. Timing optimization and power minimization methods using the concept are discussed in detail. Evaluation results obtained by proposed approach show superior performance and dramatic reduction of design period, and indicate validity of layout driven synthesis and optimization concept.
An automated tool for diagnosing simple design errors in VHDL description is presented. The tool is tested on benchmark circuits, and the results show that the error is localized precisely, after the application of a small number of specially generated test patterns. This tool is now integrated within the PREVAIL/sup TM/ system, and is being tested on industrial circuits.
The ever increasing integration of analogue and digital functions on the same IC has increased enormously the problem of testing these complex circuits. Many analogue functions are implemented using switched capacitor techniques whose inputs and outputs may be difficult to access. This paper describes a built in test technique for testing embedded SC filters. The technique proposed is called M-sequence testing and has the advantage that much of the test hardware required can be realised from registers in the digital part of the circuit.
This paper presents a novel approach supporting administrative tasks within the lifecycle of design projects. Based upon comprehensive models of design environments and design activities it combines techniques known from project management and mechanisms for design flow control. As a result it allows the planning, controlling and reviewing of design projects and supports algorithmic estimation of task durations and automatic computation of plan revisions.
This paper describes a new and highly efficient approach for weighted random pattern generation. In contrast to the state-of-the-art approaches, where input specific weights are computed, the proposed method is based on the computation of global weights. This set of a very few weights (e.g., 4 or 8) is pattern oriented and therefore, with each weight the generation of the related random patterns is uniquely specified. Starting with a deterministic test pattern set and the inherent pattern specific weights, columns or rows can be inverted such that the initial weights are maximized in order to minimize the number of random patterns. Our experiments with the prototype system POWER-TEST (Pattern Oriented WEighted Random TESTing) show that very high fault coverage can be achieved with low computation and implementation effort at low self-test hardware costs.
