This chapter provides an overview of the performance evaluation methods developed for specific subsystems. It aims to combine subsystem performance evaluation methods to deal with Multiprocessor systems-on-chip (MPSoC). MPSoCs require the integration of heterogeneous components on a single chip. The design of MPSoC architectures requires the exploration of a huge space of architectural parameters for each component. The long-term goal of this work is to build a global MPSoC performance evaluation by composing different tools. This kind of evaluation will be referred to as holistic performance evaluation. The chapter analyzes the application domain of the performance evaluation process within the systems design flow. MPSoCs are made of subsystems that may have different abstraction levels. The evaluation of a full MPSoC design containing a mixture of hardware, software and interconnect subsystems, needs to cover the evaluation of all the subsystems, at different abstraction levels.

The Handbook presents material in the form of tutorials, surveys, and technology overviews, combining fundamentals and advanced issues, with articles grouped into sections for a cohesive and comprehensive presentation. The text contains 112 contributed reports by industry experts from government, companies at the forefront of development, and some of the most renowned academic and research institutions worldwide. Several of the reports on recent developments, actual deployments, and trends cover subject matter presented to the public for the first time.

Task mapping has been a hot topic in multiprocessor system-on-chip software design for decades. During the mapping process, load balance (LB) and communication optimization have been two important performance optimization factors. This paper studies the relations between LB, interprocessor communications, and communication pipeline technique during the mapping process, and proposes an integer linear programming (ILP)-based static task mapping approach, which considers both LB and communication optimization. The approach consists of an optimized ILP model for task mapping with fewer variables compared to previous ILP mapping works. Moreover, to enhance the scalability of the ILP task mapping, the task-processor-cluster algorithm is proposed to reduce the scale of the task graph and the number of processors and then solve the coarse-grained input by the ILP mapping. To increase the adaptability of the ILP task mapping, the improved augmented $\epsilon $ -constraint method is further integrated with the ILP formulations to select the best mapping for different applications. Experimental results on a 2/4/8/16/24-CPU platform of both synthetic and real-life benchmarks demonstrate the efficiency of the proposed approach.

This chapter presents a novel method to automatically generate application-specific operating systems (OS). It provides a short review of energy consumption issues related to the OS. The chapter focuses on the OS generation in the system-on-chip (SoC) architecture. Although most of SoC applications require low-power OSs, applications requiring ultra low-power OS are sensor network and network on chip. The OS provides the application software with services such as task scheduling and synchronization, interrupt management, input/output and memory management. The input to the OS generation is the VADEL description that contains a network of hierarchical modules, communication between modules and parameters for OS generation. The code selector takes as input the list of required service names from the architecture analyzer. It uses the OS library to check service dependencies and finds all the OS elements that have dependency relation with the required services and that are compliant with the target architecture.

Communication frequency is increasing with the growing complexity of emerging embedded applications and the number of processors in the implemented multiprocessor SoC architectures. In this article, we consider the issue of communication cost reduction during multithreaded code generation from partitioned Simulink models to help designers in code optimization to improve system performance. We first propose a technique combining message aggregation and communication pipeline methods, which groups communications with the same destinations and sources and parallelizes communication and computation tasks. We also present a method to apply static analysis and dynamic emulation for efficient communication buffer allocation to further reduce synchronization cost and increase processor utilization. The existing cyclic dependency in the mapped model may hinder the effectiveness of the two techniques. We further propose a set of optimizations involving repartition with strongly connected threads to maximize the degree of communication reduction and preprocessing strategies with available delays in the model to reduce the number of communication channels that cannot be optimized. Experimental results demonstrate the advantages of the proposed optimizations with 11--143% throughput improvement.

The high demand of low-power radio transceivers for the Internet of Things drives the design of innovative wireless architectures. In this context, the energy efficiency problem arises from the strong variability of the radio channel. As a solution, we propose to dynamically optimize the receiver performance jointly with the power consumption, in order to reach a low-margin operating mode. For this purpose, we have developed an IEEE 802.15.4 Digital Baseband (DBB) with a built-in tunable subsampling mechanism. This paper describes the design and the hardware implementation of a low-complexity controller for managing this adaptive system. It explains the basic methodology and points out some practical considerations for a robust and efficient implementation. As a result, the paper shows the impact of the controller design on the baseband power consumption.

The emerging market of the Internet of Things is constrained by the energy-efficiency of each layers having a role in Wireless Personal Area Networks (WPANs). In this context, adaptivity is a key technique to address the need of low-power consumption in unpredictable environments, by providing at any time a low-margin operating mode. For this purpose, the paper presents an IEEE 802.15.4 digital baseband with a tunable computation subsampling mechanism built-in. The described architecture, simulated in a 65 nm LP-CMOS process, drains only 82.9 μA in average at its best operating point against 208 μA in normal mode. Thus, it enables a power consumption reduction of up to 58 % that can be exploited in case of favorable receiving conditions, as part of a self-adaptive wireless network.

Energy-efficient wireless communications are key enablers for the development of smart objects. New architectures with very low-power profile have to be investigated for targeting advanced implementations. In this context, the paper proposes to employ the Compressive Sensing theory for the detection of M-ary orthogonal signals, without complete recovery. This allows to lower the digital baseband computation load for almost equivalent performance. Simulations based on the IEEE 802.15.4 standard shows that the BER matches the theoretical results with a tolerable loss, depending mostly on the compression rate. Then, numerical analysis brings out some practical limitations that have to be considered when using this technique. Finally, the paper underlines the innovative use of compressive sensing for reducing the computation load during detection. This flexibility enables the selection of the most efficient operating point.

With the expansion of Internet of Things (IoT), the design of highly-integrated radio transceivers is a challenging task. The major concern is the power consumption, which is generally non-optimal due to the fluctuation of the communication channel quality. In this paper, we propose the use of downsampling techniques for decreasing the computational load of the baseband signal processing. More precisely, the paper compares two mechanisms using the IEEE 802.15.4 PHY in the 2.45 GHz band. It demonstrates that the performances remain close to the theoretical bound, even if only partial codes are used for the decoding. According to these results, it shows the impact of such techniques on the power consumption, considering a codes correlator unit. Thereby, it highlights the ability of downsampling to be used as an actuator in an adaptive baseband architecture, while preserving a good level of performances.

This title covers all software-related aspects of SoC design, from embedded and application-domain specific operating systems to system architecture for future SoC. It will give embedded software designers invaluable insights into the constraints imposed by the use of embedded software in an SoC context.

Efficient design of multiprocessor system-on-chip (MPSoC) requires early, fast, and accurate performance estimation techniques. In this paper, we present new techniques based on fine-grained code analysis to estimate accurate performance during simulation of MPSoC transaction accurate models. First, a GCC profiling tool is applied in the native simulation process. Based on the profiling result, an instruction analyzer of the target CPU architecture is proposed to analyze the cycle cost of C code under estimation. In addition, a memory analyzer is used to further estimate memory access latency including both instruction/data cache time cost and global memory access cycles. Both data and instruction cache models are proposed to estimate cache miss penalty, and a segment-based strategy is adopted to update the cache models more efficiently. Furthermore, an equalized access model is presented to imitate the memory access behavior of processors for estimating global memory access latency caused by bus contention and memory bandwidth. We have applied these techniques on an H.264 decoder application with different hardware architectures. The experimental results show that applying these techniques can obviously improve estimation accuracy of transaction accurate models close to that of the virtual prototype models, with a tolerable overhead on simulation speed.

Improvement in the quality of integrated circuit designs and a designer's productivity can be achieved by a combination of two factors: Using more structured design methodologies for extensive reuse of existing components and subsystems. It seems that 70% of new designs correspond to existing components that cannot be reused because of a lack of methodologies and tools. Providing higher level design tools allowing to start from a higher level of abstraction. After the success and the widespread acceptance of logic and RTL synthesis, the next step is behavioral synthesis, commonly called architectural or high-level synthesis. Behavioral Synthesis and Component Reuse with VHDL provides methods and techniques for VHDL based behavioral synthesis and component reuse. The goal is to develop VHDL modeling strategies for emerging behavioral synthesis tools. Special attention is given to structured and modular design methods allowing hierarchical behavioral specification and design reuse. The goal of this book is not to discuss behavioral synthesis in general or to discuss a specific tool but to describe the specific issues related to behavioral synthesis of VHDL description. This book targets designers who have to use behavioral synthesis tools or who wish to discover the real possibilities of this emerging technology. The book will also be of interest to teachers and students interested to learn or to teach VHDL based behavioral synthesis.

To address the problem of prohibitive cost of advanced fabrication technologies, one solution consists in reusing masks to address a wide range of ICs. This could be achieved by a modular circuit that can be stacked to build TSV-based 3D systems with processing performance adapted to several applications. This paper focuses on 4G wireless telecom applications. We propose a basic circuit that meets the SISO (Single Input Single Output) transmission mode. By stacking multiple instances of this same circuit, it will be possible to address several MIMO (Multiple Input Multiple Output) modes. The proposed circuit is composed of several processing units interconnected by a 3D NoC and controlled by a host processor. Compared to a 2D reference platform, the proposed circuit keeps at least the same performance and power consumption in the context of 4G telecom applications, while reducing total cost. More generally, our cost analysis shows that 3D integration efficiency depends on the size of the circuit and the stacking option (die-to-die, die-to-wafer and interposer-based stacking).

To address the problem of prohibitive costs of advanced technologies, one solution consists in reusing masks to address a wide range of systems. This could be achieved by a modular circuit that can be stacked to build 3D systems with processing performance adapted to several applications. This paper focuses on 4G wireless telecom applications. We propose a basic circuit that meets the SISO (Single Input Single Output) transmission mode. By stacking multiple instances of this same circuit, it will be possible to address several MIMO (Multiple Input Multiple Output) modes. The proposed circuit is composed of several processing units interconnected by a 3D NoC and controlled by a host processor. Compared to a 2D reference platform, the proposed circuit keeps at least the same performance and power consumption in the context of 4G telecom applications, while reducing total mask cost.

As the overall economy and semiconductor industry emerges from one of the worst recessions in years, it is time to take stock of EDA challenges and its future. This panel will focus on which challenges will surge and dominate EDA over the course of next several years and which challenges we can sell short.

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This chapter details the virtual prototype design. The virtual prototype design consists of integrating the HAL implementation into the software stack and establishing the final memory mapping. The verification of the software is performed by using classical co-simulation with instruction set simulators (ISS). The key contribution in this chapter represents the virtual prototype definition, organization, and design using SystemC for the token ring application running on the 1AX architecture, Motion JPEG running on the Diopsis RDT architecture, and H.264 encoder running on the Diopsis R2DT architecture. The Motion JPEG application is executed using ISS on different types of single processor (ARM7, ARM9, and DSP) and the H.264 encoder is simulated using ISS running on both multi-processor architecture with three ARM7 processors and single processor (ARM7 and ARM9). The simulation of the virtual prototype model allows to verify the software binary and the memory mapping.

Today, due to the increasing demand for more and more complex applications in the consumer electronic market segment, Systems-on-Chip consist of many processing elements and become larger and larger. While on-chip system designers must be able to get fast and accurate communication performance analysis for such huge systems, the simulation-based approaches are not adequate anymore. Addressing the increasing need for early performance evaluation in NoC-based system design flow, this paper presents a generic analytical method to estimate communication latencies and link-buffer utilizations for a given NoC architecture with a given application mapped on it. The accuracy of our method is experimentally compared with the results obtained from Cycle-Accurate SystemC simulations.

Due to continuously increasing system-on-chip design complexity and tight time-tomarket requirements, virtual platforms have become a widely adopted solution to achieve concurrent hardware/software design for embedded architectures. This article explains the advantages of using virtual platforms for software design on multicore/multiprocessor systemon-chip architectures. It also gives a survey of well-known key players in the field: virtual platform tools providers, design companies, and emerging standards for enabling easy intellectual property interoperability. Important research directions required to meet the current challenges of virtual platform design are also summarized.