Recently the semiconductor industry tends to develop a smaller volume device and system with lower power consumption, lower leakage current, and high speed performance. SOI technology has many unique characteristics, which is one of the most promising methods to the direction. As the semiconductor memory is concerned, the 1T-DRAM cell realized by the concept of floating body effect in a PD-SOI nMOSFET can allow the DRAM cell to be scaled down in depth with less area occupied. In this paper, we propose a new structure of 1T-DRAM cell, which has bottom buried oxide with the sidewall block oxide around its body, which can suppress the leakage current between the S/D and the body of the cell. In addition it can also improve the programming window of the 1T-DRAM cell more than 39% by utilizing its own structural characteristic
Memory has become one of the critical components in many applications. This paper presents new designs of SRAM memory circuit and architectures for applications in 3D graphics, JPEG2000, and multimedia codec. In the 3D graphics pipeline, the memory initialization is realized by modifying the circuits in the SRAM decoder and storage cell. In the bit-plane coder (BPC) of JPEG2000, we propose a new 3D memory architecture design and the corresponding circuit designs for efficient data access in processing the stripe-based bit planes. The 3D memory design can be also applied to the design of parallel-in-parallel-out transpose memory that is frequently encountered in the design of 2D DCT in JPEG and MPEG codec. We also develop a memory generator to allow for easy generation of the application-specific memory units of various sizes to be embedded in conventional cell-based design flow
The scaling of CMOS technology has significant impacts on SRAM cell - random fluctuation of electrical characteristics and substantial leakage current. The random fluctuation of electrical property causes the symmetrical 6T cell to have huge mismatch in transistor threshold voltage. Consequently, the static noise margin (Read Margin) and the write margin are degraded dramatically. The SRAM cell tends to be unstable and the low power supply operation becomes hard to achieve. Besides that, the large leakage current caused by the low threshold voltage and thin gate oxide let the sub-nano SRAM design have huge static power. This makes portable electronics applications become difficult. In this talk, several design techniques used to minimize the static power consumption will be addressed and compared first. Second, in order to increase the read/write margins of SRAM cell, the VDC (Voltage Down Converter) approach will be discussed. It is founded that by using a simple VDC design, the RM (Read Margin) and WM (Write Margin) can be significantly improved and let the SRAM design be functional in the 0.7V range. The yield of the SRAM chip can also be dramatically improved. Incorporated with a resistor-less BGR (Bandgap Reference) design, this VDC can be used for static power reduction, read margin and write margin improvement, programmable voltage and voltage clamping.
It has become 19 years, since the development of the NAND Flash started using 0.7..m rule in 1987. The speed of the scaling has been very fast and the period of the product of the new generation is less than 2 years. Now, design rule of the NAND Flash memory has become less than 70nm. There are some problems to interfere with the scaling of the memory cell. Basic idea to overcome these problems will be introduced in this talk.
A new March-based fault location and full diagnosis algorithm is proposed for word-oriented static RAMs. A March algorithm of complexity 31N, N is the number of memory words, is defined for fault detection and partial diagnosis. Then March-like algorithms of complexity 3N to 5N are used to locate the aggressor words of coupling faults (CF) and achieve full diagnosis for all unlinked static CFs. Another March-like algorithm of complexity 16logB+18, B is the number of bits in the word, is applied to locate the aggressor bit in the aggressor word. A software tool is developed for automated generation of fault syndromes for detection, partial and full diagnosis of all static unlinked faults
This paper highlights the cell current characterization of a low leakage 6T SRAM by adjusting the threshold voltages of the transistors in the memory array to reduce the standby power. Experiments using a 0.25 mum 2.5V standard CMOS process with and without the additional threshold voltage adjustment implant on a 1Mb test chip demonstrate the effectiveness. A substantial standby power reduction by an order of magnitude is achievable. However, it incurs a wider cell current variation, which is pronounced only at a lower supply voltage. As the supply voltage decreases, the percent deviation from the average value increases. This can be modeled by a simple power-law relationship. The result has important implications in both design and manufacturing of the low leakage SRAM. Comparing with the generic cell current without the additional threshold voltage adjustment, the crossover point of their percent deviations at 2V signifies two separate circuit strategies: operating at 1.5V requires larger sensing margin and operating at 2.5V enjoys better manufacturability. Hence, for the applications requiring low voltage operations, it favors a boosted supply voltage applied to a selected cell during the read access
A new test pattern, Quadruplet Checker Board (QCKBD), is proposed which enables to evaluate magnetic crosstalk from the neighbor write lines. At first, some conventional test patterns changing the write points were applied to categorize Magnetic Random Access Memory (MRAM) write errors. But magnetic crosstalk from the neighbor write lines could not be isolated by these conventional tests since magnetic crosstalk error was caused when the neighbor cell is written. Whereas the QCKBD results from 4Kb test vehicles show that magnetic crosstalk restricts the write margin. By changing the cell structure in order to suppress magnetic crosstalk, the write margin is improved from 3.3 to 7.3.
In order to ease the time-to-market pressure of flash memory, we propose a fault-pattern based diagnosis methodology that reduces the burden in yield learning. The fault-pattern based diagnosis approach is based on defect dictionary and ATE log file. The proposed diagnosis method allows product engineers to quickly isolate defect candidates. In this paper we use open/short defects to demonstrate our method. We propose a diagnostic test algorithm for flash memory based on the targeted defect models. The length of the new diagnostic test is shorter than previous ones, so diagnosis time can be reduced. Experimental results show that the diagnostic resolution of fault-pattern based method reaches 83.3% for a NOR-type flash, and 100% for a NAND-type flash. We also present a current test to improve the diagnostic resolution for NOR-type flash, so its diagnostic resolution can reach 100% as well
In this paper, one of the future nonvolatile memory candidates, SONOS with p + -poly gate, has been fully characterized in cell program/erase operation and data retention performance. Novel source-side injection programming and F-N erase schemes have been utilized on both n + - and p + -poly gate, and its characteristics are very satisfactory and can be easily used as a state-of-the-art flash memory. For data retention, our experimental result shows p + -poly does have a slower charge decay rate than does n + -poly gate. This is because of the work function difference between n + - and p + -poly gate that causes the different amount of trapped electrons between two of them. We also predict the charge loss characteristics with various baking temperature for n + - and p + -poly gate, which can tell us the concrete threshold voltage at any read delay time instead of the traditional and inaccurate long time projection from short time status
The characteristics of polysilicon-oxide-nitride-oxide-silicon (SONOS) devices with different tunnel oxides are studied. The tunnel oxide fabricated by high-temperature oxide (HTO) with additional NO annealing treatment (HTO (NO*)) has better performance than that fabricated by HTO only and in-situ steam generated oxide (ISSG) including operation window, retention, and endurance. Besides, the properties of charge-to-breakdown are also observed. The study can provide a straightforward way of reliability for future flash memory application
Testing of embedded memories, independent whether it is of volatile or non-volatile type, is based on various kinds of built-in self-test. This test solution is often driven by the fact that the system application does not provide an atspeed signal interface at the product pins. In complex SoC designs it is furthermore mandatory to do BIST as there are multiple memories of various size and organization integrated onto one chip. Given the fact that multi-site testing is state of the art even for highly complex SoCs the requirements onto the available test equipment (ATE) depend on the selection whether the product is dominated by memory or by logic/mixed signal or RF functions. This often leads to less efficient test solutions and requires multi insertion test flows in production. Here a new approach will be presented to bridge this challenging scenario. It contains a new type of signal and information handling interface between the device under test and the tester. The revolutionary change is that the ATE will act in a slave mode during a significant fraction of the manufacturing test while the DUT controls timing as well as data flow. Such new interface can serve the needs for data collection with focus on diagnosis (scan test diagnosis) at volume manufacturing as well as the complex handling of fail bit data at zero test time overhead. The basic building blocks either on-chip or in the ATE instrumentation will be explained. Especially in testing multiple embedded memories on multiple chips at the same time the throughput increase will be extraordinary.
The paper discusses the concept of dynamic data stability in the SRAM cells. It is shown that the criteria for the absolute static data stability in an SRAM cell is a sub-set of its dynamic data stability. Hence, test methods that are based on dynamic stress of the cell have limited success in discovering the defective cells. Hammer test, for example, fails to discover the faults in an SRAM cell when it is data stable in the dynamic sense but not statically data stable. It will be shown that a long cell access time can detect such faults as it reduces the effect of the dynamic data stability. This method can be combined with stressed cell methods to achieve higher accuracy. Simulation results in a 130nm CMOS technology confirm the method with a good success
Non-volatile semiconductor memory, especially Flash memory has seen explosive growth in recent years because of unceasing demand for higher performance and density for cell phone, digital still camera, camcorder, MP3, consumer electronics and automotive applications. Despite the rosy outlook, both NOR and NAND Flash technologies face steep challenges to further scale down into the sub-45nm nodes. At 45nm node both technologies confront fundamental physics limitations - the non-scalability of tunnel oxide and cross talk between floating gates. This paper examines the scaling limits for Flash memories and surveys potential solutions that promise to carry nonvolatile memories further down the Moore’s curve at 32nm node and beyond.
This paper introduces a novel procedure of identifying better representatives of faulty cells in a memory map to help judge unrepair ability and provide economic repair recommendation. These representative faulty cells, called leading elements (LE), are classified into four primary types based on their characteristics. Three specific pairs of initially identified LE are extracted for further operations, which are replacing certain LE with other better representatives and assigning the cross point faults between two certain LE as new LE. All steps of the procedure are analyzed in sequence with verification, clearly indicating that the identified LE represent both the more exact thresholds for judging unrepairability and usually the most economic repair solutions. Experiments on many example maps show that the procedure can be fast in searching 7% more LE and be applicable to accumulate data for redundancy planning afterwards.
The effect of gate oxide breakdown has long been studied in the context of device functional failure in the past. As technology node scales down to very deep submicron (VDSM) era, such an effect starts to influence the performance and power consumption of digital circuits within their lifetime. Meanwhile, process variability like threshold voltage shift due to e.g., device dopant fluctuation and/or line edge roughness effects also leads to significant shift of the parametric figures for performance and energy of these circuits at sub 100nm era. Further scaling will definitely lead to the co-existence of both effects in a single circuit. In this paper, we present the experimental analysis on the impact combining gate oxide breakdown and process variability on the energy and delay figures of SRAM cell and sense amplifier. Hspice simulations at 65nm technology node indicate a significantly larger shift in both energy and delay of these components than in the cases with either single effect when using the thinner oxide found in 45/32 nm technologies. The actual behavior of the circuits under such a situation becomes more difficult to predict and control, thus bringing a huge challenge to a successful design in the VDSM era.
The speed of DRAMs is increasing from generation to generation. This paper gives an overview of typical DRAM output timing challenges. Tight output timing specifications in the order of several 100ps are presented. Specification requirements lead to efforts to improve the output driver design. A systematic test strategy evaluates limits of automatic test equipment (ATE) overall timing accuracy (OTA) and device performance. Systematic output timing characterization data leads to guidelines for design improvements. A good characterization strategy gives a feedback to the design of specific weaknesses of output drivers and enables ATEs to test these parameters with high accuracy.
We present a ROM compiler programmable from via 1 to via n - 2, where n is the number of metal layers. The layer on which the code via is landed can be selected by the user. With the coding being able to take place as close to the topmost metal as possible, the turnaround time for a revision is shortened. In this paper, we discuss the array assembly scheme and its impacts on the design considerations by the choice of strapping period
This presentation starts with DRAM market overview, demand side DRAM bit shipment, content per box trend, followed by the DRAM density migration and the technology migration trend, including process migration, from micrometer to nanometer technology. As technology advances, 300mm fabrication and new generation products become the centerpiece of the future development of the DRAM industry. We present here worldwide 300mm capacity development forecast and the transition of DDR, DDR2, and DDR3, with a brief introduction of DDR3 features and advantages. Then we summarize the demand and supply trend of the DRAM industry. Finally, we conclude our presentation with the historical DRAM cell development and the comparison between Trench and Stack technologies.
Semiconductor Companies are continuously trying to keep their customers Happy and Satisfied with new products, new functionalities and new interfaces. To keep track on inventing products with new more facilities, Semiconductor Companies have to include much more transistors per millimeter square than ever before. Nowadays, System on Chips (SoCs) are very dense, approaching 1 billion of transistors per chip of few millimeters. Interaction of this huge number of transistors in a chip is becoming much more important than few years ago. To be specific, in current process technologies new defects mechanisms and process variation are causing complex faulty behaviours, which are creating new challenges for test experts. Moreover, embedded memories occupy a big portion of SoCs approaching nowadays 70% of total SoC area and are infringing the DFM rules, which creates even higher defect density than logic or analog blocks. This tutorial will give an overview about high quality memory testing in industrial environment, and how Semiconductor Companies are surviving in competitive markets by delivering high quality products and targeting for Zero Defect escapes for specific customers (e.g., Automotive, Medical Systems, Avionics, etc.). Also, an overview about closing the loop with memory designers and process engineers in early phase of the design is highlighted. Such loop could easily improve the test & yield of embedded memories in short market time window by taking decisive actions on layout level.
Non-Volatile Memory devices are indispensable for embedded chip/system. They are used for the storage of embedded software, which controls the operation of the chip/system. Conventionally, to embed Non-Volatile Memory devices onto a chip requires tremendous effort to develop a processing technology, which incorporates Non-Volatile Memory devices with logic devices. However, such effort requires more masking layers to be added to the logic process and thus the cost and turn around time of manufacturing considerably increases. The programmable logic Non-Volatile devices (Neobit®/NeoFlash®) offered by eMemory uses the exiting processes (Logic, Analog, Mixed-Mode, RF, HV, etc.) without or with minimum extra cost (2 additional non-critical masking layers). Neobit®/NeoFlash® offers cost-effective and fast development cycled programmable logic Non- Volatile devices to be used in embedded chip/system. Due to its simplicity and high portability, it is believed that such solutions will enable the increased applications of embedded system and over 90% of embedded chip will use programmable logic Non-Volatile device by 2010. Programmable logic Non-Volatile device become very promising in various semiconductor applications.
