One of the most critical layers in DRAM production is comprised of large arrays of dense contact holes. With more advanced nodes, the pitch shrinkage of these contact holes results in a more significant contribution of the photoresist, its processing, and resulting stochastic effects to pattern quality and yield. This becomes even more critical for 0.55NA EUV use cases, where the reduced depth of focus decreases the usable process window. Optimized photoresist processing, including etch, is one of the enablers for driving down the stochastic variation for these patterns.
We present innovative design strategies to eliminate the need for at-resolution field stitching in high-numerical aperture extreme ultraviolet lithography. For logic applications, two complementary approaches at the inter- and intra-cell levels are proposed. These include the insertion of dummy filler cells or relaxed-pitch cells, combined with metal routing blockages, which can be seamlessly implemented within a modified place-and-route flow, thereby simplifying process complexities associated with at-resolution stitching. For dynamic random access memory applications, a die aspect ratio optimization methodology is introduced to maximize mask area utilization and improve manufacturing throughput. Depending on the die arrangement in the full imaging field, two stitching scenarios are identified: an even number of dies in the Y-direction, enabling pitch-tolerant field stitching along the scribe lane, and an odd number of dies, which eliminates the need for critical-dimension-critical stitching at the stitching boundary.
Background: Multipatterning (MPT) technology is a class of technologies for integrated circuit (IC) manufacturing to make the density of features of a layer beyond the limitations of a single exposure lithography. As the semiconductor process further scales down to 2 nm and beyond, the MPT technology has emerged as the clear choice for the routing of metal layers even within the era of extreme ultraviolet lithography. The stitching technique within MPT can divide a node into multiple nodes, each of which can be assigned to different colors to prevent color conflicts. This stitching approach is essential for resolving the m-coloring problem in the real-world patterning process without increasing the number of masks or adding chip-area penalties. As the chip manufacturing process continues to shrink, triple and quadruple patterning technologies (TPT/QPT), along with automatic stitching solution, become more and more worthwhile for chip scaling. However, as the complexity of IC design escalates, identifying the optimal stitching locations for the congested routing metal layers becomes increasingly challenging. Aim: Synopsys IC Validator (ICV) provides a complete and integrated flow of TPT/QPT, featuring an innovative stitching methodology. Approach: The stitching flow consists of three key steps. Step 1 (stitch generation): generating possible effective stitches after color conflicts are detected in the initial coloring. Step 2 (link mapping): identifying spaces less than the minimum coloring distance with these stitch candidates. Step 3 (re-coloring with stitch candidates): selecting and applying valid stitches among all stitch candidates to obtain TPT/QPT-compliant layouts. Results: ICV's stitching flow for TPT/QPT has demonstrated its effectiveness in managing the dense routing metal layers of the most advanced logic technology. By employing this sophisticated and integrated approach, we can achieve stringent chip-scaling targets while maintaining acceptable routing and coloring turnaround times. Finally, our proposed stitching solution can be seamlessly extended to more complex patterning technologies with a larger number of exposure masks (i.e., five, six masks, & mldr;), as needed. Conclusions: In summary, ICV's stitching technology for the MPT lithography is a valuable and efficient solution for automatic layout-fixing and engineering change order (ECO) routing, ensuring high-quality results in the most advanced logic designs.
Background A key challenge in semiconductor 3D integration is the occurrence of small voids with diameters ranging from a few nanometers to several micrometers. Depending on the chip/package design and production process, these voids may occur across a large depth range (1 to 1000 mu m)-e.g., the typical bond interface depth in wafer-to-wafer bonding lies at a depth of 775 mu m. The standard tools to detect these deep defects are infrared microscopy, scanning acoustic microscopy (SAM), and X-ray. However, they all have limitations in resolution or penetration. Aim Here, we propose an acoustical technique named half-wavelength contact acoustic microscopy (HaWaCAM (R)) to sidestep this problem. HaWaCAM (R) consists of a 4 GHz transducer integrated on top of a custom-designed probe and uses solid-to-solid contact to couple waves into the sample, enabling a higher detectability and resolution compared with SAM. Approach In this work, we investigate the suitability of HaWaCAM (R) to detect deeply buried voids. We used the HaWaCAM (R) setup on a silicon wafer sample containing programmed voids of different sizes buried below 49 mu m of silicon. Results We show that HaWaCAM (R) successfully detects voids down to a width of 0.75 mu m at a depth of 49 mu m. The signal-to-noise ratio varied from 30 to 45 dB, 20 to 30 dB, and 15 to 30 dB for void widths of 2.5, 1, and 0.75 mu m, respectively. Conclusions We demonstrate the capability of HaWaCAM (R) to detect voids buried at large depths. We expect the current HaWaCAM (R) setup to detect voids with 2.5 mu m widths with 6 dB SNR buried below >800 mu m of silicon.
High numerical aperture (NA) extreme ultraviolet lithography enables device scaling and improves resolution. However, it also brings the challenge of reduced depth of focus (DOF) due to the optics with increased NA. New resist innovations are being targeted toward addressing this patterning challenge. We present how dry deposited and dry developed resists can be used to improve the focus window. Modulating the resist composition in the vertical direction and co-optimizing the process conditions have shown benefits in improving patterning metrics, including DOF. Test vehicles based on bright field pitch 32 nm hexagonal contact hole with 0.33 NA and pitch 18 nm line/space imaging with 0.55 NA are discussed to showcase the patterning improvements.
