Main memory carries data outside the processor’s trust boundary, so commodity systems-on-chip (SoCs) increasingly encrypt it; yet, in-line memory encryption engine itself becomes a differential power analysis (DPA) target whose key, if recovered, unlocks all of dynamic random-access memory (DRAM). We present PACE, a page-adaptive, cache-anchored memory encryption engine for RISC-V that makes nth-order DPA resistance practical and keeps cryptographic latency off the cache eviction critical path. PACE inserts a TileLink adapter between the last-level cache and the memory port and applies, per physical page, one of four policies (plaintext/confidentiality/confidentiality+integrity/+masking-order-d) selected from RISC-V page table bits through a memory-mapped control plane. Confidentiality uses counter mode whose per-line keystream is precomputed during cache residency; integrity is tree-free at the embedded operating point via on-chip counters and tags, with a live split counter block-MAC Bonsai Merkle tree for scale-out. DPA resistance is layered: ISAP-style fresh re-keying caps the data complexity per key at q≈1, and domain-oriented masking (DOM, d + 1 shares) protects the sole key processing block to order d. We implement PACE in Chisel on a Rocket SoC (Chipyard) and evaluate it with open-source tooling. A deterministic TileLink-level harness proves ciphertext-in-memory and detects tamper/replay/splice, and the live Tier-B engine (DRAM counters and per-line message authentication codes (MACs) plus an on-chip-rooted block-MAC tree) is validated from end to end on full Rocket and BOOM SoCs and on the FPGA; the masked Ascon-p S-box is proven order-d secure (d = 1, 2) under a glitch- and transition-aware model by three independent formal tools (COCO, PROLEAD, and SILVER, the last also deciding the full composability lattice and confirming exact glitch-robust order-2 probing security), with COCO extending the exact verdict to the highest synthesized order d = 3 (secure at probing orders 1–3); a simulated trace correlation power analysis (CPA) recovers the full key from an unprotected core and is defeated by masking, with a mutual information analysis confirming the N∝σ2(d+1) trace amplification law. We further realize PACE on field-programmable gate array (FPGA) silicon: the engine plus an on-chip ring oscillator power sensor is placed, routed, timing-closed at 100 MHz, and programmed on a Xilinx XC7Z020, and we drive a fixed-vs-random Test Vector Leakage Assessment (TVLA) campaign read back entirely over a JTAG (Joint Test Action Group). A multi-core configuration and a Linux control-plane driver are likewise validated. Across synthetic access patterns and named application kernels (AES, SHA-256, matrix multiplication, pointer chasing) on both in-order Rocket and out-of-order BOOM, application-level overhead is within measurement noise of plaintext for cache resident workloads (masking, in particular, is cycle-identical to plain confidentiality), and we characterize the cost of each policy, masking order, and re-keying interval, demonstrating side-channel-hardened memory encryption on open RISC-V hardware.
Modern embedded systems are vulnerable to complex data-oriented attacks that subvert not only existing control-flow integrity protections but also have dire implications on safety-critical applications. To overcome this challenge, this work proposes a secure RISC-based architecture that incorporates hardware-assisted Data-Flow Integrity (DFI) enforcement into the processor pipeline. The architecture uses tag-based metadata propagation, a Security Monitor Unit, and compiler support for static analysis in order to ensure the validity of dynamic data flows without affecting execution. A complete RTL prototype was designed and tested with MiBench and CoreMark. Results show an average performance overhead of 11.3% and a logic utilization increase of <9.2% on FPGAs, while achieving 100% detection of all attempted pointer corruption and data tampering attacks. These results indicate the efficacy of the lightweight security-aware RISC architecture as a feasible compromise between security, performance, and hardware expense in today’s embedded systems.
The interfacial adhesion strength of fine lines for flip-chip ball grid array (FCBGA) substrates is highly dependent on the surface desmear process during substrate manufacturing. However, the extremely narrow window for optimal desmear processes limits the improvement of the adhesion strength of fine lines. Herein, a polydopamine-modified epoxy build-up film substrate was fabricated to increase chemical bonding action and broaden the process window. The chemical structure, surface roughness, morphology, surface chemical state, and adhesion strength of the modified substrate were characterized. The results showed that the adhesion strength of the substrates increased from 2.2 N/cm to 4.1 N/cm under suboptimal process conditions. Meanwhile, the effect of the polydopamine deposition time on the adhesion strength of the copper-deposited epoxy resin composite films at the interfaces was systematically investigated; furthermore, the mechanisms and reasons for the increased adhesion strength and interfacial adhesion failure for the copper-deposited epoxy resin composite build-up film substrates were revealed. This work will provide guidance in both theory and experiment to enhance the interfacial adhesion force for advanced substrates in the future.
The transition from electrical to optical interconnects, enabled by the adoption of co-packaged optics (CPO) in advanced processors, is accelerating the scale-up to high volumes and redefining wafer-level test requirements. As optical interfaces migrate closer to the compute die, an increasing share of functional characterization must occur at the probe, where stringent sub-micron alignment, the mechanical stability necessary to preserve optical coupling against dynamic disturbances, and opto-electrical co-validation introduce new technical challenges. Ensuring repeatable and precise fiber-array-unit (FAU) engagement at the wafer level is therefore essential to enable scalable manufacturing of photonic-enabled processors. This paper introduces the EclipsePhotonic probe card, which embeds the Eclipse Dynamic piezoelectric positioning mechanism into a standard vertical-needle probe head as a route toward six-degree-of-freedom FAU manipulation with nanometric positioning accuracy. This architecture is designed to support repeatable coupling to on-wafer photonic structures without requiring specialized probe-head designs, thereby reducing integration complexity and addressing alignment-related yield risks. The platform is also intended to support multi-site electrical and optical probing, providing a path toward parallel test execution once the corresponding layout, optical-routing, and validation constraints are satisfied. A core innovation of the platform is its embedded sensor network, which integrates low- and higher-frequency displacement sensors, relative displacement sensors, and temperature sensors around a microcontroller-based supervisor. The vibration sensor fulfills a dual operational role: it detects environmental and test-cell disturbances that may have influenced optical coupling, providing essential context for binning decisions or targeted retest, and it contributes to probe card lifecycle monitoring by ensuring that the mechanical signature of the probe card remains within a validated operational “swim lane” throughout its service life. Recently published characterization of the underlying Eclipse Dynamic alignment engine shows that, in the production-optimized high-speed regime with effective hysteresis compensation, the Fixed Gradient routine provides the best normalized trade-off among the evaluated routines, with a normalized alignment cost of 1.44 a.u., 95.8% convergence reliability, and 99.4% of the global maximum optical coupling. These values should be interpreted as inherited algorithmic benchmarking results rather than as absolute wall-clock performance of the fully integrated sensor-augmented platform.
This paper presents an open-source miniaturised readout device designed for the wireless interrogation of passive LC sensors and wireless power transmission. The system is based on a Sparkfun RedBoard Artemis microcontroller with a custom-printed circuit board as an extension, providing a compact, low-cost alternative to expensive laboratory-grade equipment. The reader coil is excited by a signal that can be tuned digitally in both frequency and amplitude. The resonance frequency of a wirelessly coupled LC tank is detected by monitoring the voltage minimum of a rectified signal envelope, which corresponds to the impedance change of the reader inductance at resonance. Experimental validation demonstrates that the device accurately tracks resonance frequency shifts resulting from variations of the LC tank’s capacitance, performing comparably to laboratory-grade impedance analysers. Testing the influence of axial separation between the two coils up to 25 mm showed stable and identifiable voltage dips. The programmable excitation signal peak-to-peak voltage ranges from 0.81 V to 5.35 V. The device enables fully stand-alone operation with a display and navigation switch, making it suitable for untethered LC wireless sensing and actuation applications.
This work presents a comprehensive analytical and simulation-based comparison between bulk-driven (BD) and gate-driven (GD) operational transconductance amplifiers (OTAs) operating in the deep-subthreshold ultra-low-voltage regime. While BD techniques are traditionally considered unsuitable for high-performance analog design due to their lower transconductance efficiency, this study demonstrates that, when combined with self-cascode structures, BD architectures achieve competitive intrinsic gain, enhanced input common-mode range, and improved slew rate efficiency under nanoampere bias conditions. To support these claims, closed-form analytical derivations, dynamic analysis, and comprehensive Monte Carlo and PVT simulations are provided to quantify robustness and mismatch sensitivity. The results establish a systematic framework for evaluating BD versus GD architectures under identical technology and power constraints, offering practical design guidelines and optimized self-cascoded topologies for next-generation energy-autonomous systems.
This paper presents a rule-based LVS-driven methodology for parasitic RC extraction from CMOS layouts for post-layout SPICE simulation. The proposed approach operates directly within foundry-qualified rule environments, ensuring consistency with Process Design Kits (PDKs) and enabling seamless integration with existing design and verification flows without requiring field-solver execution during the production extraction flow. The methodology provides a generalized framework for deriving electrical parameters from layout geometries and is applicable to interconnects, contacts, vias, and gate structures in multilayer CMOS technologies. By decomposing conductive regions into directional components and applying geometric and Boolean operations, the method captures the impact of layout topology and process-dependent features on circuit-level behavior. In addition, a model-order reduction technique based on π-equivalent representations is introduced to simplify the resulting networks while preserving timing accuracy. This enables the scalable simulation of complex layouts with reduced computational overhead. The proposed framework supports layout optimization, variability-aware design, and process-technology co-design, particularly for mature and advanced planar nodes. The methodology is evaluated using register-file layout test cases and post-layout SPICE simulations. The results show that the proposed rule-based extraction and RC-merging flow preserve timing behavior while reducing netlist complexity.
Hyperdimensional computing (HDC) provides a highly efficient alternative to neural networks for intracranial electroencephalography (iEEG) seizure detection on edge devices with strict resource limits. While sparse HDC can significantly reduce energy use, current hardware fails to capitalize on this for two reasons. First, existing designs do not optimize the encoding architecture specifically for sparse execution, leaving potential energy savings on the table. Second, researchers often ignore the “area” problem, the large physical space high-dimensional vectors take up on a chip, which must be solved to make these devices small enough for practical edge use. This work presents a sparse HDC accelerator that bridges these gaps through three key contributions. First, we streamline the sparse encoding architecture to improve energy and area efficiency by integrating a compressed item memory (CompIM) and simplified spatial bundling. Second, to address the area bottleneck and enable true edge deployment, we systematically explore area trade-offs via sequentialization techniques, evaluating both channel folding (CF) and vector folding (VF). Third, we push efficiency even further by proposing an item-memory-free (IM-free) architecture. By replacing the baseline segmented shift binding with a standard shift binding scheme, and gracefully utilizing raw local binary pattern (LBP) codes directly as shift amounts, we completely bypass the CompIM for simultaneous area and energy savings. However, this optimization incurs a drop in detection accuracy; hence, we ultimately present two tailored configurations. First, our energy-optimized IM-free design achieves a 5.55× area and 3.08× energy improvement over the sparse HDC baseline, alongside 8.20× and 13.37× improvements over the dense baseline. Second, to prioritize clinical performance, our balanced streamlined design utilizes a channel folding factor (CFF) of 4 to preserve higher accuracy. This balanced approach achieves a 5.97× area and a 4.66× energy improvement over the dense baseline, with a 4× latency increase.
DIGOTA architectures have attracted growing interest as a means of addressing the problems that arose with the extreme miniaturization of the MOS transistor in analog design. Despite the increasing number of proposed architectures, the literature remains fragmented, with differences in design goals, structural choices, and evaluation criteria that make direct comparison difficult. This paper presents a comprehensive survey of DIGOTA architectures reported in the literature so far. This review study is organized according to key architectural characteristics, including biomedical applications, flexible electronics, and low-power amplifiers. Based on this analysis, the paper discusses major trends, common trade-offs, strengths, and limitations across current approaches. The survey also identifies open issues and promising directions for future research. By providing a structured overview of the field, this work serves as a useful reference for researchers seeking to understand, compare, and develop DIGOTA architectures.
With the increasing complexity and connectivity of modern digital systems, verification has emerged as a critical bottleneck in the design flow. Assertion-Based Verification (ABV) has proven to be one of the most effective techniques for presilicon verification. Once assertions are generated, they can be synthesized into hardware monitors and incorporated into the design debug infrastructure. Many Design-for-Debug (DfD) methodologies leverage such hardware monitors to enhance the observability and controllability of internal system behavior, thereby accelerating verification and reducing time to market. Post-silicon debugging also benefits from the improved observability provided by these monitors. Furthermore, hardware monitors can be employed during runtime to detect and report undesired behaviors. To enable the seamless use of assertions, which are originally expressed in verification languages, throughout the entire design life cycle, several assertion synthesis approaches have been proposed. The objective of this survey is to present the existing assertion synthesis methods reported in the literature, discuss their current limitations, and identify directions for future research and improvement.
Semiconductor technologies are susceptible to radiation effects. The particle incidence in susceptible areas of an integrated circuit (IC) can generate physical interactions capable of producing errors. This paper predicts the IC cross sections for Single Event Effects. The cross section is a metric that provides an IC’s susceptibility to radiation. It deals with particle source interaction and physical design volumes. This work evaluates the IC cross section, exploring the physical design characteristics of susceptible regions in logic gates. It explores particles with low LET, identifying the charge collection areas. Also, the heavy ions are used to evaluate the critical cross section range. Distinct benchmark circuits were simulated to characterize sensitivity trends. The influence of circuit input conditions along with cells’ susceptibility reveals significant findings. The results indicate a difference up to ten times between low- and high-energy particles. Consequently, predicting the IC cross section at an early stage of the design flow is essential, especially for electronics devices used in radiation environments.
For sensing applications, a complementary metal oxide semiconductor (CMOS) image sensor (CIS) with a lateral overflow integration capacitor (LOFIC) is in high demand. The LOFIC CIS can achieve high-dynamic-range (HDR) imaging by combining a low-conversion-gain (LCG) signal for large maximum signal electrons and a high-conversion-gain (HCG) signal for a low electron-referred noise floor. However, the LOFIC CIS faces challenges regarding the power consumption and circuit area when reading both HCG and LCG signals. To address these issues, this study proposes a readout circuit composed of area-efficient MOS capacitors using a folding DC operating point technique and an in-column signal selector for an on-chip HDR merger of HCG and LCG signals. A 10-bit test chip was fabricated with a 0.18 µm CMOS process with MOS capacitors. The fabricated chip maintains high linearity, achieving an integral nonlinearity (INL) of +7.17/−6.93 LSB for the HCG signal and +7.95/−7.41 LSB for the LCG signal. Furthermore, the proposed design achieves a 14.92% reduction in the average power consumption of the total readout circuit and a 36.5% reduction in the readout circuit area.
The fast expansion of the Internet of Things (IoT) has increased the need for strong security measures to protect the enormous network of interconnected devices. This paper proposes a unique approach that combines optimization, intuitive design principles, and Least Weighted Elliptic Curve Cryptography (LWECC) to improve IoT device security while reducing power consumption. The proposed optimization strategy focuses on lowering computational overhead, which is critical for IoT devices with limited energy and processing power. The proposed method significantly reduces the amount of energy required for cryptographic operations by carefully selecting appropriate elliptic curves and optimizing cryptographic algorithms, ensuring that IoT devices may continue to function without compromising security. Furthermore, by selecting elliptic curves with minimal attack vulnerability, the use of LWECC provides an additional layer of protection. This technique ensures that, even in the face of emerging threats, IoT devices remain highly resilient, reducing the chance of security breaches while preserving functionality without using excessive power. Experimental results show a power consumption of only 0.156 W and 0.25 W for memory and router topologies, respectively, with an error margin of 0.01. The stated error margin pertains to the simulation-based evaluation of transmission-level data handling within the LWECC-enabled memory/router pipeline, rather than the risk of physical memory-cell failure or fabrication yield. The value shows the maximum amount of packet/data-stream loss detected during encrypted data transfer, rather than hardware memory reliability.
This paper presents the Spike Processing Unit (SPU), a digital spiking neuron model based on a discrete-time second-order Infinite Impulse Response (IIR) filter. By constraining filter coefficients to powers of two, the SPU implements all internal operations via shift-and-add arithmetic on 6-bit signed integers, eliminating general-purpose multipliers. Unlike traditional models, computation in the SPU is fundamentally temporal; spike timing emerges from the interaction between input events and internal IIR dynamics rather than signal intensity accumulation. The model’s efficacy is evaluated through a temporal pattern discrimination task. Using Particle Swarm Optimization (PSO) within a hardware-constrained parameter space, a single SPU is optimized to emit pattern-specific spikes while remaining silent under stochastic noise. Results from cycle-accurate Python simulations and synthesizable VHDL implementations indicate that the learned temporal dynamics are preserved under hardware-constrained digital execution, supporting the feasibility of the proposed approach. This work demonstrates that discrete-time IIR-based neurons enable reliable temporal spike processing under strict quantization and arithmetic constraints.
Power converters based on gallium nitride (GaN) are progressing swiftly owing to their exceptional efficiency and tiny dimensions, boosted by high power density and fast switching capabilities. Nevertheless, these benefits are accompanied by considerable thermal management issues that impact reliability, performance, and operational lifespan. This review examines advanced thermal management approaches for high-power-density GaN power converters, including active and passive cooling technologies, sophisticated packaging designs, and the use of novel materials like graphene and diamond to improve heat dissipation. The impacts of thermal boundary resistance, self-heating phenomena, and substrate selection on thermal performance are thoroughly analyzed. Strategies for enhancing printed circuit board (PCB) layouts, thermal vias, and the use of thermal interface materials (TIMs) are also emphasized. The study highlights co-design approaches that optimize thermal resistance and layout efficiency, supporting GaN operation under high-frequency conditions. This thorough investigation offers insights into addressing the thermal challenges linked to GaN technology, promoting its adoption in forthcoming power devices.
This paper presents a novel design for a reconfigurable CDC as a multiplexed sensor fusion that converts three analog signals into digital output bits with different resolutions. The proposed reconfigurable CDC design uses the SAR technique that introduces a small chip area and low power consumption. The proposed novel CDC introduces reconfigurability by using a switching capacitive DAC that solves the problem of converting more than one analog signal with a single converter to a different number of output bits, giving better performance than previous designs. In this paper, three analog signals are used (as a case study) in a weather station to be converted. These signals are temperature, pressure, and humidity that are sensed using the BME-280 Bosch sensor. All CDC specifications are measured for each reconfigured number of output bits. The used supply voltage is 1.0 V, and the sampling frequency is 100 kHz. The 12-bit resolution consumes 2.54 µW, ENOB is 11.47 bits, and SNR equals 73.4 dB. The 8-bit resolution consumes 1.7 µW, ENOB is 7.39 bits, and SNR equals 46.24 dB. The 4-bit resolution consumes 0.68 µW, ENOB is 3.58 bits, and SNR equals 23.45 dB. The total chip area is 0.18 mm2.
This work presents an advanced electro-physical model for hydrogenated amorphous silicon (a-Si:H) Junction Field Effect Transistors (JFETs) to enable the design of devices with energy-efficient analog interface building blocks for Lab-on-Chip (LoC) systems. The presence of this device can support monolithic integration with thin-film sensors and circuit-level design through a validated compact formulation. The model accurately describes the behavior of a-Si:H JFETs addressing key physical phenomena, such as the channel thickness dependence on the gate-source voltage when the channel approaches full depletion. A comprehensive framework was developed, integrating experimental data and mathematical refinements to ensure robust predictions of JFET performance across operating regimes, including the transition toward full depletion and the associated current-limiting behavior. The model was validated through a broad set of fabricated devices, demonstrating excellent agreement with experimental data in both the linear and saturation regions. Specifically, the validation was carried out at 25 °C on 15 fabricated JFET configurations (12 nominally identical devices per configuration), using the mean characteristics of 9 devices with standard-deviation error bars. In the investigated bias range, the devices operate in a sub-µA regime (up to several hundred nA), which naturally supports µW-level dissipation for low-power interfaces. This work provides a compact, experimentally validated modeling basis for the design and optimization of a-Si:H JFET-based LoC front-end/readout circuits within technology-constrained and energy-efficient operating conditions.
Neuromorphic computing, an interdisciplinary field combining neuroscience and computer science, aims to create efficient, bio-inspired systems. Different from von Neumann architectures, neuromorphic systems integrate memory and processing units to enable parallel, event-driven computation. By simulating the behavior of biological neurons and networks, these systems excel in tasks like pattern recognition, perception, and decision-making. Neuromorphic computing chips, which operate similarly to the human brain, offer significant potential for enhancing the performance and energy efficiency of bio-inspired algorithms. This review introduces a novel five-dimensional comparative framework—process technology, scale, power consumption, neuronal models, and architectural features—that systematically categorizes and contrasts neuromorphic implementations beyond existing surveys. We analyze notable neuromorphic chips, such as BrainScaleS, SpiNNaker, TrueNorth, and Loihi, comparing their scale, power consumption, and computational models. The paper also explores the applications of neuromorphic computing chips in artificial intelligence (AI), robotics, neuroscience, and adaptive control systems, while facing challenges related to hardware limitations, algorithms, and system scalability and integration.
Sorting networks are of prime importance as circuits, with applications in sorting small data chunks, big data analytics, permuting packets, and system interconnects. Finding optimal sorting networks is a highly complex problem, and knowledge on optimal sorting networks is limited. When optimising the network depth or the number of comparators, one of the most expensive tasks is considered to be verification, that is, to verify that the candidate compare-and-swap network actually sorts the data. This grows exponentially with the size of the sorting network. However, FPGAs allow vast amounts of internal parallelism, and our presented work exploits this flexibility using dataflow techniques to achieve unparalleled amounts of speedup for sorting network verification. This work can be used in a modular way to accelerate the search for optimal sorting networks with a high number of inputs, as well for similar verification problems.
In this study, we present the design and analysis of a stacked inverter-based millimeter-wave (mmWave) power amplifier (PA) in 90 nm CMOS-targeting wideband Q-band operation. The PA employs two PMOS and two NMOS devices in a fully stacked inverter topology to distribute device stress, remove the need for an RF choke, and increase effective transconductance while preserving compact layout. A resistor ladder biases the stack near VDD/4 per device, and capacitive division steers intermediate-node swings to enable class-E-like voltage shaping at the output. Closed-form models are developed for gain, output power, drain efficiency/PAE, and linearity, alongside a small-signal stacked-ladder formulation that quantifies stress sharing and the impedance presented to the matching networks; L/T network synthesis relations are provided to co-optimize bandwidth and insertion loss. Post-layout simulation in 90 nm CMOS shows |S21| = 10 dB at 39.84 GHz with 3 dB bandwidth from 36.8 to 42.4 GHz, peak PAE of 18.38% near 41 GHz, and saturated output power Psat=8.67 dBm at VDD=4 V, with S11<−15 dB and reverse isolation ≈−16 dB. The layout occupies 1.6×1.6 mm2 and draws 31.08 mW. Robustness is validated via a 200-run Monte Carlo showing tight clustering of Psat and PAE, sensitivity sweeps identifying sizing/tolerance trade-offs (±10% devices/passives), and EM co-simulation of on-chip passives indicating only minor loss/shift relative to schematic while preserving the target bandwidth and efficiency. The results demonstrate a balanced gain–efficiency–power trade-off with layout-aware resilience, positioning stacked-inverter CMOS PAs as a power- and area-efficient solution for mmWave front-ends.
