Accurate pole–zero determination is essential for predicting the frequency response, stability, and bandwidth of analog circuits. Conventional transfer function derivations based on nodal or mesh analysis, however, often produce lengthy symbolic expressions and provide limited physical insight, particularly for high-order networks. This paper presents a generalized order-reduction method for deriving the transfer functions of linear time-invariant analog circuits with constant coefficients. The proposed approach decomposes a higher-order network into lower-order configurations and determines the coefficients of its characteristic and zero polynomials by selectively suppressing or isolating energy storage elements. First-order time constants are obtained from the equivalent resistance or conductance associated with each capacitor or inductor. Higher-order coefficients are then evaluated by systematically considering combinations of energy storage elements and successively reducing the network order. The relationship between driving-point impedance and admittance is also employed to establish a unified procedure for determining poles and zeros. The method is applicable to passive and active RLC circuits, including networks containing dependent sources and transistor small-signal models. Several representative examples, ranging from elementary RC networks to higher-order active circuits, are analyzed to demonstrate the derivation procedure and its ability to retain explicit dependence on circuit parameters. Compared with direct symbolic expansion, the proposed framework reduces algebraic manipulation while preserving the physical interpretation of the resulting coefficients. The method therefore provides a systematic and design-oriented tool for transfer function characterization and pole–zero analysis of linear analog circuits.
The continuous scaling of semiconductor technology is facing increasing physical limitations, making conventional geometry-driven scaling insufficient for future ultra-scale computing systems. Electronic-photonic integrated circuits (EPICs) provide a promising approach to overcome interconnect and bandwidth bottlenecks; however, existing EPIC design methodologies still suffer from fragmented optimization across different abstraction levels. In this work, we propose a τ-Law-driven design methodology based on temporal scaling for ultra-scale electronic-photonic integrated circuits. By introducing the time constant τ as a unified optimization objective, the proposed framework enables coordinated optimization across device, circuit, chip, and system levels. A mathematical formulation is established to integrate electronic interconnect delay, optical propagation delay, and electro-optical/opto-electrical conversion delays into a unified temporal optimization model. A quantitative evaluation methodology based on representative parameters reported in previous EPIC studies is further developed to analyze the effectiveness of τ-oriented optimization. The proposed approach is further validated using a proof-of-concept electronic-photonic link, where different configurations are experimentally compared in terms of end-to-end latency. The quantitative and experimental results show that coordinated reduction in multiple latency contributions can reduce system-level latency compared with conventional independent optimization, providing a potential pathway beyond geometry-driven scaling toward scalable and automated EPIC design for future photonic computing and heterogeneous integration systems.
As smart sensing applications grow rapidly, the IoT edge architectures need to support low latency, make decisions with little memory, power, and communication resources while preserving the privacy of the data. But traditional cloud-based IoT solutions come with transmission delay, increased energy consumption, and privacy issues because of the constant transfer of raw data. In this paper, we propose a privacy-preserving TinyML-driven IoT edge architecture that enables real-time smart sensing and autonomous AI-based control. The proposed framework includes on-device sensor pre-processing, lightweight TinyML inference, adaptive model selection, encrypted feature-level communication, trust-aware decision validation, and local control execution. Raw data streams from the sensors are also processed locally, and only compact encrypted features or a summary of the decisions are sent if necessary to minimize privacy exposure. The experimental evaluation reveals that the proposed architecture has an accuracy of 97.4%, an F1 score of 96.9%, and a secure-event detection rate of 98.1% and reduces the inference latency by 14.8%, the energy consumption by 4.1 mJ per inference and the amount of data transmitted by 74.5% compared to conventional edge-cloud processing. Results show that the proposed architecture is a scalable, privacy-aware, and energy-efficient solution for real-time autonomous IoT control of smart environments with limited resources.
This article presents a finite impulse response (FIR) moving-average filter for validating noisy analog signals. While the conventional sliding-window implementation is computationally efficient, it requires storing the last N − 1 samples, leading to significant memory usage for large windows. To address this limitation, an alternative method is proposed that avoids full sample history storage by integrating the filter state with incoming samples. Under slowly varying input conditions, the proposed circuit reproduces the behavior of a conventional moving-average FIR filter. The approach is applied to a charger controller for validating the termination current of a lithium-ion battery, demonstrating reduced memory requirements and simplified implementation.
Main memory carries data outside the processor’s trust boundary, so commodity systems-on-chip (SoCs) increasingly encrypt it; yet, in-line memory encryption engine itself becomes a differential power analysis (DPA) target whose key, if recovered, unlocks all of dynamic random-access memory (DRAM). We present PACE, a page-adaptive, cache-anchored memory encryption engine for RISC-V that makes nth-order DPA resistance practical and keeps cryptographic latency off the cache eviction critical path. PACE inserts a TileLink adapter between the last-level cache and the memory port and applies, per physical page, one of four policies (plaintext/confidentiality/confidentiality+integrity/+masking-order-d) selected from RISC-V page table bits through a memory-mapped control plane. Confidentiality uses counter mode whose per-line keystream is precomputed during cache residency; integrity is tree-free at the embedded operating point via on-chip counters and tags, with a live split counter block-MAC Bonsai Merkle tree for scale-out. DPA resistance is layered: ISAP-style fresh re-keying caps the data complexity per key at q≈1, and domain-oriented masking (DOM, d + 1 shares) protects the sole key processing block to order d. We implement PACE in Chisel on a Rocket SoC (Chipyard) and evaluate it with open-source tooling. A deterministic TileLink-level harness proves ciphertext-in-memory and detects tamper/replay/splice, and the live Tier-B engine (DRAM counters and per-line message authentication codes (MACs) plus an on-chip-rooted block-MAC tree) is validated from end to end on full Rocket and BOOM SoCs and on the FPGA; the masked Ascon-p S-box is proven order-d secure (d = 1, 2) under a glitch- and transition-aware model by three independent formal tools (COCO, PROLEAD, and SILVER, the last also deciding the full composability lattice and confirming exact glitch-robust order-2 probing security), with COCO extending the exact verdict to the highest synthesized order d = 3 (secure at probing orders 1–3); a simulated trace correlation power analysis (CPA) recovers the full key from an unprotected core and is defeated by masking, with a mutual information analysis confirming the N∝σ2(d+1) trace amplification law. We further realize PACE on field-programmable gate array (FPGA) silicon: the engine plus an on-chip ring oscillator power sensor is placed, routed, timing-closed at 100 MHz, and programmed on a Xilinx XC7Z020, and we drive a fixed-vs-random Test Vector Leakage Assessment (TVLA) campaign read back entirely over a JTAG (Joint Test Action Group). A multi-core configuration and a Linux control-plane driver are likewise validated. Across synthetic access patterns and named application kernels (AES, SHA-256, matrix multiplication, pointer chasing) on both in-order Rocket and out-of-order BOOM, application-level overhead is within measurement noise of plaintext for cache resident workloads (masking, in particular, is cycle-identical to plain confidentiality), and we characterize the cost of each policy, masking order, and re-keying interval, demonstrating side-channel-hardened memory encryption on open RISC-V hardware.
