Fatigue damage of solder joints is a serious reliability concern in electronic packaging. In this study, a flip chip package was modeled to investigate the effects of underfill material properties and BT substrate thickness on solder joint reliability. The CTE was found to have the main effect and matching CTE between underfill and solder joint is the most important consideration in the selection of underfill material. This paper also presents a creep fatigue life prediction model for thermal cycling. The model is generated by correlating nonlinear finite element analysis with experimentally measured thermal fatigue lives of flip chip packages. This creep fatigue model may be used in parametric studies assessing the influence of flip chip or FCOB design parameters on solder fatigue life.
System-On-Package (SOP) can reduce package size, increase functionality, improve performance, and reduce cost by embedding passives in a multilayered high-density wiring (HDW) substrate structure and by bonding flip-chips on top of integrated high-density wiring substrate. Due to stringent warpage requirements, new base substrate materials with a high modulus are being explored for sequentially processing the multilayers on top. The substrate should also have a Coefficient of Thermal Expansion (CTE) that is close to that of the die, and the matched CTE will facilitate no-underfill attach Flip-Chips on SOP substrates. One major concern with the high-modulus, matched CTE substrate is the potential interfacial delamination between different dielectric and metallization layers built-up on top of the base substrate. The objective of this paper is to evaluate the possibility of interfacial delamination between metallization and dielectric layers built on top of the base substrate. An analytical model and a numerical model have been developed to calculate the energy release rate for interfacial delamination propagation under thermal load. To be able to predict interlayer delamination propagation, the interfacial fracture toughness of copper/ViaLux 81 PDDF has been measured with specially designed sandwich type double cantilever beam (DCB) specimens. The energy release rate (ERR) obtained from the analysis was compared with the interfacial fracture toughness, and the results indicate that there is minimal delamination growth under the given thermal load conditions. Also, test vehicles have been fabricated and tested to experimentally validate the results from the models.
In this paper, a simple but very practical analytical model is presented to calculate the induced strains in the solder joints of underfilled flip chip assemblies. This model is only a rough approximation of the real distribution in the solder joints, but the model explains very well how several design parameters influence the solder joint reliability and why an underfill with high elastic modulus and a CTE in the range of 15-25 ppm/°C is optimal for the solder joint reliability. It also proves that the solder joint reliability of underfilled assemblies is almost independent on the chip size. The distance between the outer joint and the chip edge is a influential parameter.
The thermomechanical warpage or vertical deflection of microelectronic packages due to temperature change is caused by the mismatch in the coefficients of thermal expansion between vertically asymmetric layers of materials. The structure of many microelectronic packages may be characterized as a multi-layered plate consisting of two regions, that of a die area and a mold area. Physical observation of various packages demonstrates that these two regions cause the package to exhibit dual curvatures, which are approximated using closed form sets of algebraic equations. The resulting technique, termed the dual-curvature approach, predicts the thermomechanical warpage of packages composed of temperature-dependent materials and may be extended for application to packages having a diverse range of geometries. The accuracy of the dual-curvature approach is assessed for square, single-die packages by means of three-dimensional, finite element simulations at nine in-plane locations. It is shown that the dual-curvature approach significantly improves the thermomechanical warpage prediction of microelectronic packages relative to earlier analytical models.
Microelectronic science and technology is shrinking the world. Advanced packaging and systems make bulk electronic devices miniaturized and multi-functioned. In fact, mobile, wireless, and hand-held products are becoming the mainstream of personal, as well as business practice. This new trend makes warpage, one of the main assembly issues in electronic packaging, more critical to product yield and reliability. Warpage could affect flip chip solder joint attachment in first level interconnections, as well as misregistration between the packages and the printed wiring boards. The shadow moire technique has been widely used to measure warpage. However, inherent configurations limit its use on certain scenarios. In comparison to the shadow moire approach, the projection moire method provides several advantages. It is more suited for measuring flatness of surfaces with components. The grating sizes can be easily adjusted, thus making it versatile for measuring various board and chip sizes and details. Without the grating glass, which is a substantial heat inertia, the sample can be heated more evenly during the thermal process. Also, using a laser as the light source makes the system less sensitive to ambient light. In this paper, a novel system based on the projection moire technique is presented. The system setup is described and analyzed to reveal its advantages, resolution, and accuracy. A set of experimental results of a variety of sample sizes will be shown. It is concluded that this projection moire system, which is integrated with an oven system, is a powerful tool to study warpage of printed wiring boards and integrated circuit packages.
Numerical predictive accuracy is investigated for transient component heat transfer using a computational fluid dynamics (CFD) code dedicated to the thermal analysis of electronic equipment. The test cases are based on a single printed circuit board (PCB)-mounted, 160-lead PQFP component, analyzed in still-air, and both 1 and 2.25 m/s forced airflows. Three types of transient operating conditions are considered, namely (i) component dynamic power dissipation in fixed ambient conditions, (ii) passive component operation in dynamic ambient conditions, and (iii) combined component dynamic power dissipation in varying ambient conditions. Benchmark criteria are based on component junction temperature and component-PCB surface temperature, measured using thermal test dies and infrared thermography respectively. Using both nominal component/PCB geometry dimensions and material properties, component junction temperature is found to be accurately predicted for component dynamic power dissipation, in both fixed and varying ambient air temperature conditions.
This paper presents an experimental study on the reliability of eutectic Sn-Pb (Sn63/Pb37) solder bumps and the reliability of eutectic Sn-Pb bumped flip chip (FC) assemblies mounted on an FR-4 substrate. The growth kinetics of Sn-Ni intermetallic compound, Ni 3 Sn 4 , on eutectic Sn-Pb solder bumped chips with Ni(P)/Au metallization was investigated. The growth of Ni 3 Sn 4 was found to be proportional to the square root of thermal aging time. The activation energy of Ni 3 Sn 4 growth was 31.23 kJlmol (0.32eV). Accelerated reliability tests revealed that even after 1000 cycles of the temperature cycling, the shear strength of eutectic Sn-Pb solder bumps did not change, while the shear strength showed a tendency to decrease after an extended period of high temperature storage at 125°C. The fracture mechanism for the shear test of solder bumps was a combination of fracture at the under-bump metallization/solder bump interface and in the bulk solder. For eutectic Sn-Pb solder bumped FC assemblies, accelerated reliability tests (temperature cycling (TC), high temperature storage and temperature humidity) indicated that the first 100 cycles or the first 100 hours was the most critical stage of the tests for the assemblies. In general, the temperature cycling was the most severe test. The premature failure of certain assemblies was due to weak interconnections between the bumps and the board due to cold soldering and small voids near the solder joints. For the specimens that exhibited drastic failure under the TC test, the delamination between the underfill and the passivation of the chip was the dominating mechanism.
Much of the required background technical work to achieve successful implementation of lead-free soldering has been carried out, or, is now underway. Process issues are also being addressed successfully through work with an ever-increasing range of lead-free product releases. Future work is expected to focus more on the development of standards, test methods and supply chain issues that are affected by the move to lead-free, and this paper outlines some of the activities underway in the US and Europe regarding, e.g. tin whisker and solderability test methods for lead-free, lead-level definition and component MSL. The need for global co-operation for successful outcome from all work in this area is highlighted and examples provided of activities designed to develop lead-free technology roadmaps outlining guidelines for introduction timescales and technical issues requiring resolution.
Thermo-mechanical deformations of flip-chip interconnections on an organic substrate are investigated by microscopic moire interferometry. A detailed experimental procedure for microscopic moire experiments is described and the effect of specimen preparation is discussed. Two identical packages, one with and the other without underfill, are investigated. They are subjected to a uniform thermal loading and thermally induced displacement fields are documented by microscopic moire interferometry. The ultra-high displacement measurement sensitivity and the microscopic spatial resolution of the method allow a detailed analysis of solder bumps. The normal and shear strains (averaged along the vertical centerlines) at each solder bump are calculated from the displacement fields. The experimental results confirms the effect of underfill on the solder bump strains; the average shear strains are reduced by an order of magnitude and the average normal strains in the direction perpendicular to the chip thickness becomes compressive.
With the RoHS/WEEE Directives potentially outlawing lead from electronics produced and imported in the EU by 2006 or 2007 [1] and foreign competition driving the implementation of lead-free electronics assembly around the world, additional questions regarding the integrity and reliability of various alloy compositions continue to arise. In short, the issue of which alloy(s) to select continues to loom. This paper shall take an in-depth view of Sn/Ag, Sn/Ag/Cu and Sn/Cu alloys and compare the reliability testing results and process considerations for these. First, however, this paper will address the often-misunderstood issue of lead contamination of lead-free assemblies.
The heat transfer performance of various fin types was investigated in Part I of this paper1. Among these, the staggered plate fin array proved to be potentially most suitable for maximizing heat transfer and minimizing pressure drop. In the present study, CFD simulations were performed to determine optimum heatsink parameters such as fin thickness, spanwise pitch and lengthwise pitch. In most practical forced convection situations, using aluminum heatsinks, the airflow is laminar and can be modeled quite adequately using a two-dimensional periodic geometry and isothermal boundary conditions. Therefore, CFD simulations can provide a high degree of confidence in approximating optimum geometries which then can be experimentally verified. The previous work has been extended to develop a CFD-based optimization procedure by generating a database of non-dimensional heat transfer coefficients and friction factors for a range of various independent geometric variables. These included fin/base area ratio and lengthwise/spanwise pitch ratio and each combination was evaluated at several Reynolds numbers. This resulted in a general correlation encompassing the full range of geometric variables for a practical range of Reynolds numbers. The optimum geometry provided minimum thermal resistance at a fixed set of heatsink dimensions and operating conditions.
The last years have witnessed an explosive growing demand for all those electronic products, which can be jointly referred to as mobile electronics. To fulfill such a development rate in the worldwide market, the smaller, cheaper and faster philosophy in the microelectronics packaging industry needs to be pursued with ever increasing efforts. The most suitable packaging solution from this standpoint is mostly identified as the Flip Chip connection technology. In this environment, the Celestica Italia Packaging and Technology Development Group performed a qualification run on Multichip Module Laminates (MCM-Ls). Two Flip Chip attach concepts, different in the did passivation, the under bump metallurgy and the array geometry, were evaluated on the same Sequential Build-up (SBU) substrate, with the devices reliability being the most important monitored property. It has been reported that the most detrimental effects on reliability come from the underfill delamination and from a problem related to the eutectic SnPb solder alloys after multiple reflows: the solder extrusion, otherwise called Amoeba phenomenon. The solution to these problems is vital for the Flip Chip technology: the successfull actions have regarded the fluxes, the reflow profiles, the surfaces cleanliness but especially the underfill. The latter represents the most influential aspect, even for the future Flip Chip evolution steps: the reworkability and the no-flow fluxing capability.
Solder applied in the molten state was used as a thermal interface material between copper surfaces. The effect of the solder thickness on the heat transfer between the copper surfaces was studied by measuring the thermal contact conductance using the laser flash method. Increasing the thickness of solder from 10 to 30 mm was found to increase the heat transfer time (temperature rise time) by 25%. The effect is akin to replacing solder with an interface material that is 80% lower in thermal conductivity. It is also akin to decreasing the thermal contact conductance of the solder-copper interface by 70%. Thus, minimization of the solder thickness is recommended in practice.
An IC component socket is an electromechanical system that provides a separable connection between an electronic component and a Printed Circuit Board. IC component sockets provide many advantages in IC design, selection, assembly, test, upgrade, and maintenance, and they have found extensive application in the microelectronics industry, However, some challenges exist for their applications. Sockets introduce extra contact interfaces, degradation of which raises reliability concerns. Sockets also add extra electrical signal path and occupy additional spaces. The trends towards higher I/O and finer pitch of electronic devices put more stringent requirements on the design and application of sockets. This paper presents an overview of the application and benefits of IC component sockets as well as the challenges facing their application and future development.
Thermal resistance measurements on power chip slug-up and slug-down configurations are performed in this work. Two different packages set up are analyzed to reduce the contact thermal resistance effects. Cooling transient behavior is analyzed and an analytical expression with two time constants is shown to be suitable to describe the measured transient with good approximation. Thermal resistances and heat capacitances are evaluated from the equivalent electrical circuit. Constraints to use slug-up configuration instead of slug-down are established in this paper.
The solid-state intermetallic compound layer growth behavior between a Au-Pt-Pd thick film coating and two Pb-free solder compositions, 91.84Sn-3.33Ag-4.83Bi (wt. %) and 86.85Sn-3.15Ag5.0Bi-5.0Au, was evaluated for aging times of 10 hours to 5000 hours and temperatures of 55°C, 75°C, 85°C, 100°C, 135°C, and 170°C. The rate kinetics of intermetallic compound layer growth for the Sn-Ag-Bilthick film couples exhibited a time exponent, n, of 0.74±0.08 and an apparent activation energy, Dd Pd reflecting the thick film composition. The rate kinetics of intermetallic compound layer growth for the Sn-Ag-Bi-Aulthick film couples exhibited values of n and AH equal to 0.63±0.08 and 87±6 kJlmol, respectively. The intermetallic compound layer composition was AuSn 4 at the early stages of aging, but then duplicated the (Au, Pt, Pd)/Sn 4 chemistry after further aging. The faster intermetallic compound layer growth rate associated with the Sn-Ag-Bi-Au solder was caused by the incorporation of AuSn 4 particles from the solder matrix, into the advancing layer.
Passive integration can be highly rewarding in terms of miniaturization, but also in terms of performance. A very convincing example is the integration of supply-line decoupling in RF front- end modules. It will be shown that a more powerful decoupling concept can be implemented by using one single low-loss capacitor on silicon, replacing conventional SMD-based decoupling using discrete ceramic capacitors.
This research work faced the challenges from both miniaturization and environmental demands by focusing on the reliability and processability of lead-free flip chip components on high-density organic substrates. Ternary Sn/Ag/Cu alloy was used as the solder bump material for lead-free flip chip devices, while the reference samples had eutectic Sn/Pb solder bumps. High densityPWBs (Printed Wiring Board) with RCCu (Resin Coated Copper) build-up layers and Ni/Au surface finish were used as test substrates. Combinations of two flux and two capillary-flow underfill materials were used in both conventional Sn/Pb and lead-free SMD (Surface Mount Device) processes to assemble test vehicles. Reflow was done in air. Post assembly solderability and solder joint voiding were inspected by X-ray and optical microscope. Samples were subjected to two company specific reliability tests, thermal cycling and mechanical shock test, after which samples were analyzed by cross sectioning and scanning electron microscope (SEM). Underfill voiding was determined using acoustic microscopy. Clear differences in flux material performances in conjunction with Pb-free solder bumps were noticed. Differences in solder joint reliability were further observed during thermal cycling. In addition, success of the underfilling process was noticed to have a major impact on component reliability. In the end a set of suitable materials and process parameters for lead-free flip chip SMD assembly was found. Thermal cycling performance of the best Pb-free combination turned out to be equally good with the best eutectic Sn/Pb case. Also mechanical shock resistance of lead-free components was found to be equal with the reference samples.
Anisotropic conductive adhesive films (ACF) were used to attach daisy-chained test chips on FR-4 substrates. The feasibility of ACF joining was studied since it is a potential method for fine-pitch bare-die attachment on low-cost organic substrates. Four types of test chips were used, each having a pitch of different size. One of the chips had an area array structure, one had a staggered structure, while the others had a peripheral structure. The reliability of the flip chip joints was evaluated by subjecting the test chips to a temperature cycling test and to a preceding reflow aging test. The joints were studied by electrical measurements and scanning electron microscope. The alignment of the chips was confirmed with an x-ray microscope. Low resistance values were obtained in the flip chip joining process. However, it is evident that coplanarity of the substrate and the chip is important for the bonding quality. During the reflow aging test and the reliability tests some of the tested samples seemed to fail due to stresses that had induced during the bonding process. The reason for the failures was a too high bonding pressure. By decreasing the bonding pressure, reliability of these test chip types was improved.
The creep analyses of solder-bumped wafer level chip scale packages (WLCSP) on build-up printed circuit boards (PCB) with microvias subjected to thermal cyclic loading are presented. The emphasis of this study is placed on the effects of the thickness of the conventional PCB with a microvia build-up layer on the solder joint reliability of the WLCSP assembly. The 62Sn-2Ag-36Pb solder joints are assumed to follow the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and creep shear strain hysteresis loops, shear stress range, creep shear strain range, and creep strain energy density range at different locations in the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of the solder-bumped WLCSP on build-up PCB with microvia circuits. It is found that, due to the large coefficient of thermal expansion of the build-up resin, the effects of thickness of the conventional PCB with microvia build-up layer become much more significant than that without the microvia build-up layer.
