With the rapid scaling of CMOS devices towards the nanoscale regime as facilitated by lithography and strain engineering, the impact of parasitic series resistance is becoming a bigger issue. The need for shallower junctions to meet the short channel control requirements of the scaled transistors also aggravates the series resistance problem. Advanced technologies like millisecond laser anneal, which produce abrupt, highly activated junctions with negligible diffusion, are being proposed to meet junction requirements of 45nm technology node and beyond. But integrating the millisecond anneals into an existing spike baseline CMOS flow has not yet been fruitful. The increased overlap resistance due to the lack of lateral diffusion in the case of millisecond anneals is considered to offset the benefits of the otherwise abrupt and highly activated junctions. Thus for successful implementation of these advanced anneal technologies it is essential to understand the relative contributions of different components of series resistance and how it is impacted by the different USJ parameters like gate-source/drain overlap, lateral abruptness, junction depth and peak active doping concentration.
The development of Si-based tunneling-based static random access memory (TSRAM) has been described. This multi-institutional research endeavor has successfully demonstrated for the first time an integrated TSRAM that utilizes Si/SiGe resonant interband tunnel diode (RITD) and conventional NMOS. The memory cell exhibits a bistable latching operation at a low power supply voltage below 0.5 V. The key to success in the tunnel diode-based novel memory research at RIT is mutual collaboration between the institutions from the universities, government, and industry, which provides a hotbed for technological innovations and creativity.
The projected growth in successful commercialization of nanoscience products and technologies will be slowed without an adequately trained force of technician-level skilled workers. To this end, Dakota County Technical College (DCTC), a two year school in Rosemount, MN received in 2004 an NSF ATE grant to develop a nanoscience training program. The program consists of 3 semesters of coursework at DCTC in various aspects of nanotechnology, followed by a capstone semester at the University of Minnesota (UM). The capstone semester consists of 4 lecture-based courses and 3 lab courses. One of the lab courses is a fabrication course taking place in the UM Nanofabrication Center cleanroom facility. At the conclusion of the capstone semester the students graduate from DCTC with a AAS degree in Nanoscience Technology, and also have 16 credits from the University of MN.
Equipment costs for semiconductor fabrication can be millions of dollars just to get started, not to mention the specialized facility expenses required to house such intricate equipment. Specialized facilities such as clean-rooms, special exhaust systems, cryo-pumps, and gas cylinder storage are a huge investment and sometimes hard to justify for undergraduate education. Chemical usage and disposal can also be a considerable expense. Very few institutions can even afford an undergraduate microelectronics laboratory due to the high start-up costs, high equipment costs and continuous and constant maintenance of such equipment. Many colleges have acquired used equipment through donations from industry. However, donated equipment from industry is not always the most feasible option for small colleges with limited budgets and resources. The technical costs of keeping the equipment going can be expensive, not to mention the difficulty of obtaining parts on used industrial equipment. Through a recent New York State Science, Technology, and Academic Research (NYSTARreg) grant opportunity, obtained in collaborations with Alfred University and Rochester Institute of Technology, Alfred State College, a small technical college in rural western New York, has started its own low budget undergraduate microelectronics laboratory facility at a fraction of the cost of comparable industrial equipment. This new undergraduate microelectronics laboratory at Alfred State College has been equipped with Modu-Labtrade semiconductor device manufacturing equipment, which gives students realistic exposure to the semiconductor planer processes. Oxidation, diffusion, photolithography, etch, and vapor deposition stations allow the students the opportunity to design, fabricate, and test their own simple diffused resistors and PMOS devices while gaining experience in microelectronic fabrication techniques. The Microelectronics Laboratory at Alfred State College gives students a realistic experience in semiconductor manufacturing processes. An important concept of this laboratory is hands-on training. Although it is unlikely that the students will work with this type of equipment in industry, the understanding of general processes gained through laboratory experiences will prepare them to either continue their education in the microelectronics field or work in a modern industrial laboratory. Mask layers can be designed on just about any good quality CAD program. Individual layers can be printed out on transparent paper using a good quality laser printer. Diffused resistor and PMOS devices can be designed, fabricated and tested without spending millions of dollars. Functional resistors and aluminum gate PMOSFET transistors have been successfully fabricated, even though the device sizes are 100-1000 times larger than typical devices fabricated in a clean-room facility. This grant has also led to collaboration with other institutions such as Alfred University and Rochester Institute of Technology who have provided technical expertise and faculty training. Student field trips have enhanced the students' overall experience. With Modu-Lab microelectronics laboratory equipment, IC design and fabrication at the undergraduate level is now a feasible proposition for small undergraduate technical colleges.
A process for fabrication of 0.25 mum CMOS transistors has been demonstrated. NMOS transistors with drain current of 177 muA/mum at VG=VD=2.5 V and a PMOS transistors with drain current of 131 muA/mum at VG=VD=-2.5 V are reported. The threshold voltages are 1.0 V for the NMOS and -0.735 V for the PMOS transistors. The mask defined gate lengths are 0.5 mum and 0.6 mum for the NMOS and PMOS, respectively. Through a photoresist trimming process, the poly gate lengths are 0.25 mum and 0.35 mum or smaller. Electrical extraction of the gate lengths should yield effective gate lengths of 0.25 mum or smaller. These are the smallest transistors ever fabricated in the SMFL at RIT. Large off-state leakage is reported for the NMOS due to drain leakage induced by implant damage or aggressive titanium silicide formation. A better understanding of this leakage is being investigated and process recommendations given.
Lateral extended-drain MOS transistors (DMOS) are very sensitive to the well and reduced surface field (RESURF) implant critical dimensions (CDs) as well as the layer-to-layer alignment (overlay). The photoresist that is used for the well and RESURF implants of the DMOS was originally highly dependant on reticle transmission (RT). This caused significant variability in the P-channel DMOS (PDMOS) performance, while the N-channel DMOS (NDMOS) performance remained stable. The lithography solutions to improve the robustness of the DMOS structures are discussed in this paper.
Summary form only given. Continuing a trend that began with RTA, anneals continue to shrink in time and increase in temperature. The latest developments are with either flash lamp anneals in the millisecond regime or laser anneals which can be as short as nanoseconds. From a modeling perspective, there are three key challenges in accomplishing of accurately modeling these anneal cycles. First, whenever the substrate is used as a heat sink, the spatial variation of temperature is important. Most process simulators do not allow for this. This paper have addressed this and it has been fixed in FLOOPS over the last two years. This paper discuss techniques employed to minimize computational overhead in doing this. Second, the simulator must solve the heat flow equation to help generate the spatial and temporal variation of temperature. FLOOPS' scripting language is well suited to this task, and built preliminary models that help predict the onset of melting, for example. Finally, these models need to be calibrated. Can equilibrium models of heat transport be used at this time and length scale? How critical is carrier transport to the heat removal? Preliminary experimental and simulation results are presented from this regime that indicate where the pressing problems exist.
In this paper we review the use of a 3- dimensional MEMS fabrication process to prototype long stroke (>10 mum) actuators as are required for use in future adaptive optics systems in astronomy and vision science. The electrochemical fabrication (EFABtrade) process that was used creates metal micro- structures by electroplating multiple, independently patterned layers. The process has the design freedom of rapid prototyping where multiple patterned layers are stacked to build structures with virtually any desired geometry, but in contrast has much greater precision, the capability for batch fabrication and provides parts in engineering materials such as nickel. The design freedom enabled by this process has been used to make both parallel plate and comb drive actuator deformable mirror designs that can have large vertical heights of up to 1 mm. As the thickness of the sacrificial layers used to release the actuator is specified by the designer, rather than by constraints of the fabrication process, the design of large- stroke actuators is straightforward and does not require any new process development. Since the number of material layers in the EFABtrade process is also specified by the designer it has been possible to gang multiple parallel plate actuators together to decrease the voltage required for long-stroke actuators.
Tensile and compressive stressed nitride liners have been used to increase the carrier mobility in n-channel and p-channel silicon transistors respectively. Simulations indicate how much of the stress in the film is transferred to the channel region and the magnitude of the stress in different directions. A simple bulk piezoresistive model was used to estimate the effect on carrier mobility. It is shown in the case of the n-channel transistors that the enhancement is due to the vertical stress component whereas in the case of p-channel devices the enhancement is due to the in-plane stresses. The effect of different process conditions such as film stress, thickness and method of deposition, on mobility enhancement, was also characterized. It is shown that the enhancement saturates with increasing nitride thickness but scales proportionally with the film stress. Detailed studies of the effect of the circuit layout on the final channel stress allow the critical layout parameters to be identified. The variation of device performance with the layout parameters is quantified and can be used to define design rules as well as equations to modify the device characteristics based on layout.
UAF's Office of Electronic Miniaturization (OEM) has successfully transferred technology and established a prototyping chip scale packaging line in Alaska. This was accomplished by carefully managing each operational interface in the academic environment consistent with our mission. Our program offers significant benefits to the University of Alaska system, its academic partners at other universities, governmental agencies that support our activities, the community and its many industrial partners. Chip Scale Packaging is a very successful technology particularly in the consumer electronics sector. It has a proven track record. It has not penetrated as well in high value systems, entrepreneurial technologies, and government sector electronics. Our facility offers an excellent opportunity to apply CSP technologies to many unexplored areas without requiring high volume commitments. OEM is keenly interested in collaborative R&D as well as pilot projects.
A semi custom design flow was used to implement and fabricate an analog circuit. The pixel level detector circuit was designed on a sea-of-gates called an analog-leaf-cell. Cadence Tools was used to design the schematic, layout, and simulate the analog circuit. Once the layout and schematic has been verified (LVS) on Cadence tools, a post extraction simulation is observed. When all specifications have been reached, the circuit design is ready to be fabricated and is sent out to MOSIS. Eight weeks later, the integrated circuit is fabricated and packaged into an IC chip and returned to students to be tested.
We have developed a simplified 2-mask n-type Metal Oxide Semiconductor (NMOS) transistor process design and verification module for electrical engineering students enrolled in the Microelectronic Manufacturing Methods class/laboratory at San Jose State University. We have run this module for three years and have found that the simplified process allows the students to learn more because they have the time to design the process fabricate and test in one semester. Student learning is also enhanced because it allows students to make and correct mistakes in the processing the devices. We have also found that the simplified process saves time in process development of more complex processes, by reducing the number of photolithography steps required to fabricate a transistor.
Analytical and numerical gate capacitance models with polysilicon (poly) depletion effect are studied by directly solving the coupled Poisson equations on the poly and silicon sides. The poly depletion effect is known to significantly reduce surface potential, channel current and gate capacitance values. Different oxide thicknesses and doping levels of the MOS device are studied, and the final analytical gate capacitance model exhibits an excellent fit with numerical data. The analytical model is determined using asymptotic methods. The models presented here give accurate results for the poly depletion effect and this new information may be used to improve SPICE circuit simulations in advanced VLSI since the gate depletion effect is significant in current nanoscale MOSFET devices.
A model including the presence and effect of discrete quantum energy levels and trap states in nanocrystals is proposed in order to describe the anomalous peaks observed in current-voltage characteristics of emerging Si quantum dot based floating gate flash memory cells. The model is employed to investigate the effect of energy levels in quantum dots with a size distribution in the range of 0 to 12 nm in explaining the charging dynamics and current versus time characteristics. The simulated results are in close agreement with the experimental results. It is speculated that the additional peaks observed in the experimental current versus voltage characteristics above threshold voltage are because of the filling up of nanocrystals with more than one electron into quantum levels, shifted to higher energy levels due to the increase in charging energy determined by self capacitance.
This work is derived from the implementation of design proposed by Whitney J. Townsend, Mitchell A. Thornton and Parag K. Lala in 'On-line error detection in a carry-free adder' (2004). The circuit was implemented using AMI06 process to function at 200 MHz clock. The observations made from the implementation were studied and a more generalized, simple and cost effective error detecting technique is proposed.
The University of California at Berkeley is proceeding with construction of a new nanofabrication laboratory - the CITRIS Nanolab. This new facility is a key component of the College of Engineering's CITRIS research center - the Center for Information Technology Research in the Interest of Society. The new lab will enable world class faculty research and stimulate creative partnerships with industry to address nanoscale CMOS electronics, nanoelectromechanical systems (NEMS), integration of opto and bioelectronics, and nano/micro/macro interface technologies. This laboratory will be the successor to The Berkeley Microlab and will continue and expand the Microlab tradition of a professionally managed, shared laboratory resource open to all academic researchers and supported on a recharge basis to insure the lowest possible barrier to entry. This presentation will provide an overview of the design and planning process with specific commentary on some of the challenges unique to the academic laboratory. Sample questions that will be addressed are as follows. How do you define facility and utility needs when future research requests are unknown? How do you efficiently translate the extensive industry experience of design consultants to a university situation? Is it possible to communicate directly with the architect and design team when working within the procedural confines of a large state university? Construction budget versus fit-up budget - are there strategies to take advantage of the Capital Projects process? Value engineering - does it provide either? And finally, is it possible to build a research laboratory this decade without including the word nano in the facility name?
The models presented by Lu and Taur, for lightly doped double gate and surround gate MOSFETs each require numerical solution of a transcendental equation. In this paper we present compact solutions for the equations based on the Lambert function. These solutions are shown to be accurate compared with exact numerical solutions.
Lithography has been eagerly explored into nanoscale beyond sub-micrometer in the fields of leading-edge technology applications. NNFC (National NanoFab Center) has specially concentrated on direct electron beam lithography and nanoimprint which are flexible and effective methods to be applicable to sub-100 nm patterning. Nanoscaled FinFET and MRAM(magnetic RAM) were evaluated, using hybrid e-beam lithography (double masking method, mix & matching method), i.e. optical exposure tool used to reduce the total patterning time of direct electron beam. The results from these patterning methods were able to fabricate the world's smallest transistor, 5 nm FinFET and to adapt new material and device structure to magnetic device. Also 50 nm (line & space) fabrication capability of UV imprint template (stamp in UV nanoimprint) is demonstrated in this paper.
An ultra low power receiver operating in 2.4GHz ISM band is designed using 90nm CMOS PTM with a IV supply voltage. This direct conversion receiver has an integrated noise figure of 4.15 dB in the 1kHz to 10MHz band. The input referred IP3 for offset of 100MHz is -22.4dBm. The LO leakage to the RF port is less than -148dB. A base-band gain stage and buffer are used to provide a reasonable output impedance and power gain. With this, input and output are matched to 50 Omega and 500 Omega with both S11 and S22 being better than -25dB. The LNA, mixers and the base-band stages with the biasing network consume less than 1.1 mW.
A new national laboratory for optoelectronics located in Wuhan, China is introduced and its collaboration model with Georgia Tech is outlined. Their joint effort is establishing an international platform for scholars from the world to do research and education on new frontiers of photonics and electronics.
