Wideband gap devices present several challenges to device simulation. First, the minority carrier population is small and presents challenges to precision in the calculations. Second, the negative velocity field relationship due to carriers scattering into an upper band with higher mass can create convergence issues. Third, electron and hole traps can be important to the response and are often implemented as a delta function in energy. This can create convergence issues when small changes in the Fermi level create large changes in occupancy. This is made harder when, as in standard Scharfetter-Gummel, the solution variable is concentration. The Fermi level has to be derived in a complicated way from the concentration. Fourth, in many cases these devices are used in power applications and the break down voltage is a critical figure of merit. Break down is difficult to simulate since it is an abrupt change in current flow with a small change in applied voltage. Current collapse provides a similar challenge in simulation. Approaches to these issues will be discussed and demonstrated.

High Electron Mobility Transistors (HEMTs) are widely used in aerospace systems for their high efficiency and inherent radiation tolerance, yet heavy ion strikes can still induce significant damage and performance degradation. This work investigates the origin of current collapse observed in AlGaN/GaN HEMTs exposed to 8.4 MeV Bi ions over a range of fluences. The hypothesis is that heavy-ion damage creates a localized region of neutral electron traps near the gate–drain edge, coinciding with the device’s highest electric-field stress. These traps capture electrons and form a persistent negative charge distribution that depletes the 2DEG channel, suppressing drain current. DC-biased irradiation measurements confirm this behavior, showing increasing collapse with increasing fluence and field strength. A TCAD model calibrated to non-irradiated devices reproduces this mechanism and provides a quantitative explanation for the observed current collapse phenomenon.

The General Antiparticle Spectrometer (GAPS) Antarctic long duration balloon mission is scheduled for launch during the austral summer of 2024-25.Its novel detection technique, based on exotic atom formation, excitation, and decay, is specifically designed for the detection of slow moving cosmic antiprotons and antideuterons.Such antinuclei are predicted by a wide variety of allowed dark matter models, as well as other astrophysical theories like primordial black holes.There are two main components of the GAPS instrument: a large-area tracker and a surrounding time-of-flight system (TOF).The combination of these two systems allows GAPS to effectively differentiate between species of negatively-charged antinuclei and determine the energy deposition, velocity, and trajectory of particles interacting with the detector.This contribution will focus on the TOF, which determines the velocity of the incoming antiparticle and provides the trigger to the experiment.We will give an overview of the TOF detector, an explanation of relevant electronics, and a report on its construction and preliminary performance.The TOF is composed of 160 thin plastic scintillator paddles ranging in length from 1.5 to 1.8 meters.At each paddle end, signals from six silicon photomultipliers are combined to produce two copies of the resulting waveform: one to form the trigger and one for data readout.This design is optimized for low mass and fast data acquisition while still maintaining good light collection.

Accurate and fast Fermi-Dirac integral approximations are used in semiconductor device simulators to compute carrier concentrations where Boltzmann statistics cannot be applied. A similar integral can be used to compute carrier densities in the subgap region of a superconductor. The primary difference between the two integrals is the density of states (DOS) functional used. Electrons and holes in semiconductors use the spherical band approximation yielding a DOS functional proportional to the square root of state energy ( $E$ ). Superconductors in the subgap region can be modeled with a DOS of the form $(1-\frac{E^{2}}{\Delta ^{2}})^{-0.5}$ . A short series approximation using Gaussian quadrature is computed for the superconductor DOS integral. Short series approximations are also applied to the Fréchet derivatives of the integral with respect to its parameters. All short series approximations will be compared against numeric integration solutions and results in a six hundred fold reduction in integration time. A table containing the short series approximation roots and weights is given. Error plots are shown for the short series approximations at different temperatures for the niobium pair-breaking potential energy.

Dopant profiles near the semiconductor–oxide interface are critical for microelectronic device performance. As the incorporation of Si1−xGex into transistors continues to increase, it is necessary to understand the behavior of dopants in Si1−xGex. In this paper, the diffusion and electrical activation of phosphorus within a strained, single-crystal Si0.7Ge0.3 layer on Si during oxidation are reported. Both layers were uniformly doped, in situ, with an average phosphorus concentration of 4 × 1019 atoms/cm3. After high-temperature oxidation, secondary ion mass spectrometry measurements revealed that the bulk of the phosphorus diffuses out of only the SiGe layer and segregates at the oxidizing SiGe–SiO2 interface. Hall effect measurements corroborate the observed phosphorus loss and show that the phosphorus diffusing to the oxidizing interface is electrically inactive. Through density functional theory (DFT) calculations, it is shown that phosphorus interstitials prefer sites near the SiGe–SiO2 interface. Finally, based on a combination of experimental data and DFT calculations, we propose that the phosphorus atoms are displaced from their lattice sites by Ge interstitials that are generated during SiGe oxidation. The phosphorus atoms then migrate toward the SiGe–SiO2 interface through a novel mechanism of hopping between Ge sites as P–Ge split interstitials. Once they reach the interface, they are electrically inactive, potentially in the form of interstitial clusters or as part of the reconstructed interface or oxide.

Technology Computer Aided Design (TCAD) is being developed for superconductor electronics (SCE). The AlO $_{x}$ tunnel barriers used in SCE have thicknesses on the order of the surface roughness of sputtered niobium. Surface roughness is not included in a standard CMOS TCAD process simulator and is among the unique modules needed for SCE. An empirical model for surface roughness is developed for TCAD process simulators. This model is merged with the existing sputtering module and coupled with chemical mechanical polishing and aluminum oxidation to generate process-simulated structures of the Nb/Al-AlO $_{x}$ /Nb junction stack. Electrical simulations of these junctions are used to extract room temperature conductance. The inherent statistical variation of the proposed surface roughness model lends itself to large scale parallel simulation of thousands of junctions. Statistical simulations are performed and statistical analysis is given.

In five and a half years, the ColdFlux project under the IARPA SuperTools program pushed the boundaries of digital and analog superconductor electronic design automation (S-EDA) tools. The SuperTools program demanded significant beyond-state-of-the-art deliverables in four main areas: RTL synthesis, architectures, and verification; analog design and layout synthesis; physical design and test; and technology CAD and cell library design. Through the work of academic groups scattered over four continents, the ColdFlux effort forged into a powerful set of open-source and commercial S-EDA tools unlike any before, rivaled only by a commercial toolchain from Synopsys under the same SuperTools umbrella. We present an overview of the tools from where we started to the eventual project deliverables. These include powerful simulation and extraction engines, magnetic field and flux trapping analysis, advanced clocking methods, multi-chip interface extraction and verification, unified multi-layer design-rule compliant track blocks for automated place and route of both rapid single flux quantum (RSFQ) and adiabatic quantum-flux-parametron (AQFP) cells, models and tools for validation and test, multi-bit single flux quantum (SFQ) cells, architecture innovations for full CPU designs and more. Comprehensive cell libraries and a process design kit (PDK) were developed with the ColdFlux tools. The AQFP cell library features a logically rich collection of 80+ cells, including 3- and 5-input logic gates, signal-driving boosters, and refined RSFQ-to-AQFP interfaces, while the RSFQ library has 30+ cells. Finally, we discuss how the full toolchain enables and enhances the superconductor IC design process.

In this study, the response to a heavy-ion strike and the resulting single effect burnout on beta-Ga 2 O 3 Schottky diodes with biased field rings is investigated via TCAD. The model used to simulate the device under high-reverse bias is validated using experimental current-voltage (I-V) curves. A field ring configuration for the device demonstrates an improved charge removal after simulated heavy-ion strikes. If the time scale for charge removal is faster than single event burnout, this can be an effective mechanism for reducing the effect of single ion strikes. This study explores various configurations of the termination structure and shows the impact of different design parameters in terms of a transient response after the ion strike.

A recently discovered, enhanced Ge diffusion mechanism along the oxidizing interface of Si/SiGe nanostructures has enabled the formation of single-crystal Si nanowires and quantum dots embedded in a defect-free, single-crystal SiGe matrix. Here, we report oxidation studies of Si/SiGe nanofins aimed at gaining a better understanding of this novel diffusion mechanism. A superlattice of alternating Si/Si0.7Ge0.3 layers was grown and patterned into fins. After oxidation of the fins, the rate of Ge diffusion down the Si/SiO2 interface was measured through the analysis of HAADF-STEM images. The activation energy for the diffusion of Ge down the sidewall was found to be 1.1 eV, which is less than one-quarter of the activation energy previously reported for Ge diffusion in bulk Si. Through a combination of experiments and DFT calculations, we propose that the redistribution of Ge occurs by diffusion along the Si/SiO2 interface followed by a reintroduction into substitutional positions in the crystalline Si.

Ga2O3 is expected to show similar radiation resistance as GaN and SiC, considering their average bond strengths. However, this is not enough to explain the orders of magnitude difference of the relative resistance to radiation damage of these materials compared to GaAs and dynamic annealing of defects is much more effective in Ga2O3. Octahedral gallium monovacancies are the main defects produced under most radiation conditions because of the larger cross-section for interaction compared to oxygen vacancies. Proton irradiation introduces two main paramagnetic defects in Ga2O3, which are stable at room temperature. Charge carrier removal can be explained by Fermi-level pinning far from the conduction band minimum due to gallium interstitials (Ga i ), vacancies (VGa), and antisites (GaO). With few experimental or simulation studies on single event effects (SEE) in Ga2O3 , it is apparent that while other wide bandgap semiconductors like SiC and GaN are robust against displacement damage and total ionizing dose, they display significant vulnerability to single event effects at high Linear Energy Transfer (LET) and at much lower biases than expected. We have analyzed the transient response of β-Ga2O3 rectifiers to heavy-ion strikes via TCAD simulations. Using field metal rings improves the breakdown voltage and biasing those rings can help control the breakdown voltage. Such biased rings help in the removal of the charge deposited by the ion strike.

Some packaging technologies of electronic devices introduce compressive biaxial stress and variable vertical stress. In unipolar MOS devices, stress variations typically only linearly affect drain current via carrier mobility. Collector currents of bipolar devices are additionally affected by variations in intrinsic carrier concentration. This leads to increased variability of key device parameters in the compressive stress regime. Reducing package-induced compressive stress, or inducing tensile stress, should improve device variability due to local stress variations.

By modeling the propagation of a seed layer with various crystal orientations, this study explores the influence of process variations on grain formation with the help of a physics-based process simulator. Grain boundaries allow easy diffusion of foreign atoms through the lattice, which causes Al to move inside the Nb bottom electrode layer and more interestingly, O to penetrate through the Al layer during oxidation and create a barrier with non-uniform thickness. In addition to thickness variations, the grain structure exhibited by Nb and Al can cause significant suppression of supercurrent at the boundaries depending on the degree of lattice mismatch, impurity deposition, etc. This work details the process simulation of grain boundary formation and aims to provide geometrical models that may be used in the simulation of device performance to account for process-induced variations.

It has been hypothesized that the variation of the critical currents in Nb/Al-AlOx/Nb junctions is due to, among other effects, the presence of grain boundaries in the system. Motivated by this, we examine the effect of grain boundaries on the critical current of a Josephson junction. We assume that the hopping amplitudes are dependent on the interatomic distance and derive a physically realistic model of distance-dependent hopping amplitudes. We find that the presence of a grain boundary and associated disorder is responsible for a very large drop in the critical current relative to a clean system. We also find that when a tunnel barrier is present, grain boundaries cause substantial variations in the critical currents due to the disordered hoppings near the tunnel barrier. We discuss the applicability of these results to Josephson junctions presently intended for use in superconducting electronics applications.

The understanding and availability of quantitative measurements of the diffusion of dopants and impurities in Ga2O3 are currently at an early stage. In this work, we summarize what is known about the diffusivity of the common donor dopants, Sn, Ge, and Si, as well as some of the deep acceptors, N, Fe, and Mg, and donors, Ir. Two commonly encountered interstitial impurities are H and F, the former through growth and processing ambients and the latter through its use in plasmas used for stripping dielectrics from Ga2O3. Both are found to have high diffusion coefficients and an effect on electrical conductivity, and H shows anisotropy in its diffusion behavior. Si, Ge, and Sn implanted into bulk β-Ga2O3 at total doses from 2 × 1013 to 2 × 1015 cm−2 and annealed at 1100 °C for 10–120 s in either O2 or N2 ambients showed a significant effect of the annealing ambient on the donor's diffusivity. In the case of O2 annealing, there was extensive redistribution of the Si, Sn, and Ge across the entire dose range, while, in sharp contrast, the use of N2 annealing suppressed this diffusion. The N2 ambient also suppressed loss of dopants to the surface, with >90% of the initial dose retained after annealing at 1100 °C for 120 s, compared to 66%–77% with O2 anneals under the same conditions.

This project sought to develop a fundamental understanding of the mechanisms underlying a newly observed enhanced germanium (Ge) diffusion process in silicon germanium (SiGe) semiconductor nanostructures during thermal oxidation. Using a combinati on of oxidation - diffusion experiments, high resolution imaging, and theoretical modeling, a model for the enhanced Ge diffusion mechanism was proposed . Additionally, a nanofabrication approach utilizing this enhanced Ge diffusion mechanism was shown to be applicable to arbitrary 3D shapes, leading to the fabrication of stacked silicon quantum dots embedded in SiGe nanopillars. A new wet etch - based method for preparing 3D nanostructures for high - resolution imaging free of obscuring material or damage was als o developed. These results enable a new method for the controlled and scalable fabrication of on - chip silicon nanostructures with sub - 10 nm dimensions needed for next generation microelectronics, including low energy electronics, quantum computing, sensors , and integrated photonics.

The high breakdown voltage and low on-state resistance of Schottky rectifiers fabricated on β-Ga2O3 leads to low switching losses, making them attractive for power inverters. One of the main goals is to achieve high forward currents, requiring the fabrication of large area (>1 cm2) devices in order to keep the current density below the threshold for thermally driven failure. A problem encountered during the measurement of these larger area devices is the dependence of current spreading on the probe size, resistance, number, and geometry, which leads to lower currents than expected. We demonstrate how a multiprobe array (6 × 8 mm2) provides a means of mitigating this effect and measure a single sweep forward current up to 135 A on a 1.15 cm2 rectifier fabricated on a vertical Ga2O3 structure. Technology computer-aided design simulations using the floods code, a self-consistent partial differential equation solver, provide a systematic insight into the role of probe placement, size (40–4120 μm), number (1–5), and the sheet resistance of the metal contact on the resultant current-voltage characteristics of the rectifiers.

We report the development of a process/device simulation platform to model superconductor electronics. The process simulator leverages the back-end modeling capabilities of Florida object-oriented process/device/reliability simulator (FLOOXS) and builds on the existing models to simulate processes specific to Josephson junction (JJ) fabrication. The device simulator uses the process generated models and computes the normal-state electrical properties of a Nb/Al-AlO/Nb JJ. It is used to predict key operational figures of merit and how they vary with changes in process models. By integrating the process and device simulation tools, this research aims to offer an environment for the simulation of JJ circuits.