Germanium-Tin is emerging as a material exhibiting excellent photonic properties. Here we demonstrate optical initialization and readout of spins in this intriguing group IV semiconductor alloy and report on spin quantum beats between Zeeman-split levels under an external magnetic field. Our optical experiments reveal robust spin orientation in a wide temperature range and a persistent spin lifetime that approaches the ns regime at room temperature. Besides important insights into nonradiative recombination pathways, our findings disclose a rich spin physics in novel epitaxial structures directly grown on a conventional Si substrate. This introduces a viable route towards the synergic enrichment of the group IV semiconductor toolbox with advanced spintronics and photonic capabilities.
A Schottky split gate technique is used to form lateral quantum dots in the two-dimensional electron gases of a high-mobility Si/SiGe heterostructure. e-beam defined palladium gates show Schottky barriers with very well controlled leakage currents. At low temperatures we observe Coulomb-blockade and stability diamonds on lateral quantum dots containing less than 25 electrons. The experiments demonstrate that, in contrast to recent reports, Schottky gates are a feasible approach for the fabrication and integration of single electron transistors in the strained Si/SiGe heterostructure.
In this paper, we presented a comparative study of the HBT reliability of scaled 200GHz SiGe:C quasi self-aligned HBTs integrated in a 0.13mum BiCMOS process with airgap DTI. The influence of scaling and airgap DTI under the three stress conditions (reverse emitter-base current stress, very high forward current stress and mixed-mode stress) on the reliability performance is reported. It was demonstrated that for all three stress regimes, only limited increase in the base current degradation was measured and no change in the collector current has been observed. Despite the lateral scaling of the device and higher self-heating due to the airgap DTI, the base current degradation remains limited under the specified stress conditions
As high doping concentrations and high Ge contents are implemented in the base regions of SiGe heterojunction bipolar transistors (HBTs) to improve device performance, neutral base recombination (NBR) is also simultaneously enhanced. The enhanced NBR can severely degrade the current gain values of SiGe HBTs and thus needs to be carefully considered in device design. In this paper, a new analytical expression for the current gain of SiGe HBTs is derived to include the NBR component in the base current. The new current gain expression indicates that the maximum achievable current gain of SiGe HBTs is limited by the NBR and can be realized via optimization of the Ge profile. The analyses of the current gain of SiGe HBTs employing high base doping concentrations and high Ge contents are verified with MEDICI simulations.
We report the fabrication of a novel substrate platform for the monolithic integration of Si-based CMOS and GaAs-based optoelectronic devices. This platform, which we refer to as silicon on lattice-engineered substrate (SOLES), consists of a compositionally graded SiGe buffer buried underneath a silicon-on-insulator (SOI) structure, all fabricated on a Si substrate
We have developed a model of the time dependence of asymmetric strain generation in Si/SiGe bilayers on compliant substrates, and established a process window for maximum strain asymmetry. The resulting uniaxial silicon strain of 0.75% tension is well-controlled and uniform across the SOI islands
In a Si/Si1−xGex/Si(1 0 0) heterostructure patterned into a shape striped in the ⟨1 1 0⟩ direction, strain control of capping Si and Si1−xGex layers is investigated. The Raman scattering analysis of the stripe-patterned Si/Si1−xGex/Si(1 0 0) heterostructure indicates strain relaxation in the Si1−xGex layer and introduction of tensile strain into the capping Si layer by submicron stripe patterning. It is found that the degree of strain relaxation in the Si1−xGex layer is strongly dependent on the stripe width, the capping Si layer thickness and the Si1−xGex layer thickness. Four-terminal resistivity measurement of the strain-controlled Si/Si1−xGex/Si(1 0 0) heterostructure shows an increase of the electron and hole conductivity for the tensile strained capping Si layer and a decrease of the hole conductivity for the partially relaxed Si1−xGex layer.
By using electron-cyclotron resonance (ECR) plasma chemical vapour deposition (CVD), epitaxial growth of highly strained Si on 84%-relaxed Ge/Si(100) without substrate heating has been investigated. For a Si thickness of 1.7 nm, the deposited surface is atomically flat, and the strain (ratio of change in the lattice constant to strain-free lattice constant) is about 4%. This value indicates that the strained Si lattice is matched to the relaxed Ge lattice. Furthermore, it is found that the heterostructure of strained Si/Ge is thermally stable up to 600 degrees C.
This paper presents results on conventional, deep sub-micron short-channel Ge p-and nFET devices with a HiK/MG gate stack and NiGe source/drain regions. It is shown that the mobility enhancement observed in long channel Ge pFETs as compared to Si pFETs, can indeed result in deep sub-micron Ge devices with a higher drive
Strain engineering using lattice-mismatched S/D in transistors and their combination with other stressors and optimum surface/channel orientations is very attractive and important for the continued improvement of CMOS performance in addition to device scaling
In this paper, we present a compact impulse generator that is fabricated in an inexpensive ATMEL SiGe HBT technology (Schuppen et al., 2001). The realized circuit exhibits pulses with adjustable peak-to-peak amplitudes of up to 530mV. The corresponding broadband spectrum of the ultra-short pulses is centered around 5.7GHz
The emitter stripe width scaling issues for power SiGe HBTs are fully investigated in this work. Both theoretical and experimental results show that the fmax of power SiGe HBTs heavily depends on the emitter stripe width. Different from high speed device design principle, downscale of emitter stripe width is not always valid to improve the performance of power devices due to the presence of significant interconnect resistance. Instead, an optimal emitter stripe width exists, which is decided by both base sheet resistance and total emitter area. Employing a high base doping concentration and with "optimal" emitter stripe width design, the state-of-the-art power SiGe HBTs were successfully developed
We investigated the effect of dopant implantation and thermal annealing on substitution carbon concentration of Si:C epitaxial film. While spike annealing at T=1050 degC results in slight loss of substitution carbon (0.6%) but maintains high crystalline, phosphorus implantation induces significant loss of substitution carbon and a change of carbon depth profile. It is also observed that very abrupt junction can be formed in a Si:C epitaxial film
Through 1D device simulations it has been shown that there is some advantage to engineering the shape of the collector profile in SiGe HBT's but only in certain regimes. Power law profiles are shown to be superior to a flat profile only for low breakdown cases. For high-breakdown devices there is little or no advantage to shaping the profile. For the low breakdown case, profiles with their dose distributed more on the subcollector side and less on the base side are superior although it is difficult to keep adding dose ad infinitum to these types of profiles so some balance must be struck between the total dose necessary and the shape of profile used
