A compact model based on the Lambert function is used to describe I-V-T characteristics of Schottky Barrier Diodes (SBDs) with gated-edge termination (GET) with either SiN or SiO/AlO as GET dielectric. Electrical parameters obtained from this model enable Schottky barrier height (SBH) assessment. It will be shown that fluctuations are about 17% in both cases. Similar interface state density (from ideality factor) is obtained which is consistent with previous work and validates this approach as an interesting method to model these GET-SBDs.

Este trabajo tiene como objetivo estudiar la degradación de los diodos de barrera Schottky (SBD) con una terminación de borde cerrado (GET) bajo condiciones de estrés en estado de encendido en tecnologías de 200V y 650V. Después de todos los experimentos de estrés, se observa un comportamiento recuperable, que indica el atrapamiento de cargas en defectos preexistentes y no creación de nuevas trampas. Un análisis estadístico amplio demuestra una mayor confiabilidad y una vida útil más larga en comparación con trabajos anteriores en una tecnología de 200 V. Para la tecnología de 650V, se analizaron variaciones en el ánodo como una doble capa GET y el uso de Al2O3/SiO2 como dieléctrico. Se obtuvo una menor degradación total en el segundo caso gracias a la compensación entre los mecanismos de resistencia de encendido (RON) y voltaje de encendido (VTON). Se observan algunas diferencias sistemáticas en la degradación de los parámetros según la ubicación de la oblea, probablemente causadas por variaciones relacionadas con el proceso. Mediante el uso de la técnica de pares coincidentes (MP), se ha demostrado que se pueden obtener distribuciones de probabilidad caracterizadas por pendientes de Weibull únicas sobre la oblea que podrían permitir una mejor caracterización de la confiabilidad intrínseca de estos dispositivos.

Development of integration of different components with GaN-based technologies has been gaining traction in recently. Among these, diodes play important roles in GaN power ICs. For this work, a fabrication approach for integrating a Schottky barrier diode (SBD) with a p-GaN enhancement (E-mode) for 200 V switching application is demonstrated. The integrated SBD with 30-mm width shows a low forward voltage (V-f) with more than 10A and 6A at V-ac = 3 V at 25 degrees C and 150 degrees C, respectively. Additionally, the devices show a stable ON-resistance (R-ON) (<20% increase) up to 200 V at 25 degrees C/150 degrees C under pulsed IV characterization and OFF-state stress, pointing out the robust stability for integrated GET-SBDs on a power p-GaN HEMT platform.

In this work, we demonstrate enhancement-mode regrown p-GaN gate devices with high threshold voltage as well as a robust forward time-dependent gate breakdown (TDGB) stability. The regrown p-GaN gate HEMTs are fabricated with two different AlGaN barriers. Devices with 16nm Al0.235 Ga0.765 N yield a $\text{V}_{\text {TH}}$ of 1.5V and a high threshold voltage ( $\text{V}_{\text {TH}}$ ) of 2.7V is observed for 7nm AlGaN along with a gate breakdown voltage of more than 10V. Lastly, the regrown p-GaN gate HEMTs with 7nm AlGaN barrier demonstrate an operating $\text{V}_{\text {G}}$ of 7.46V and 7V for 1% failure rate of 10-year lifetime at 150°C and 25°C, which is amongst the highest values compared to the reported literature for regrown p-GaN gate HEMTs.

This paper demonstrates a 200 V GaN-on-SOI smart power integrated circuits (ICs) platform developped on 200 mm substrates. Depletion-mode (d-mode) MIS-HEMTs and Gated-Edge-Termination Schottky barrier diodes (GET-SBDs) have been successfully integrated in an enhancement-mode (e-mode) HEMT technology baseline. A variety of low-voltage analog/logic devices and passive components further supports the GaN ICs platform. These results significantly contribute to monolithic GaN integration for power ICs and create key opportunities for the development of GaN power circuits and complex converter topologies.

The degradation of Schottky Barrier Diodes (SBDs) with a Gated Edge Termination (GET) under on-state stress conditions is studied for a 650 V GaN-on-Si technology. Reliability metric techniques previously used in MOS-HEMTs are applied in this work due to a similar MIS gate stack architecture in GET-SBDs. Here, the density of traps is analyzed in GET structures where the dielectric is either Si3N4 (nitride-based) or a stack of Al2O3/SiO2 (oxide-based). Statistical analysis across two wafers indicates some systematic differences in turn-on voltage degradation depending on wafer location, likely caused by process-related variations. Under 1000 s stress time and ON-state voltage, the number of trapped charges in nitride-based dielectric devices keeps increasing. This suggests an ongoing dielectric degradation. On the other hand, Al2O3/SiO2 dielectric devices with an Al-based interfacial layer (IL) exhibit less process-induced variability across the wafer along with a lower density of trapped charges compared with nitride-based dielectric diodes under the same stress conditions suggesting better reliability and process improvement.

To investigate the defects from the gate regrowth process, samples with and without regrowth p‐GaN process are fabricated by metalorganic chemical vapor deposition (MOCVD). The DC characteristics indicate larger gate leakage (Igs) between the GaN channel and the p‐GaN gate in the regrowth sample than in the nonregrowth counterpart. In addition, significant Si/O impurities are introduced by the regrowth process at the interface between channel and regrown AlGaN barrier. The low‐frequency noise (LFN) measurement and deep‐level transient spectroscopy (DLTS) are further carried out to investigate the defectivity at the AlGaN barrier and channel interface, giving a 2–3 times higher border trap density in the AlGaN barrier (depth ≈5 nm from the channel interface) and a 10 times increase in interface trap density at the channel interface, corresponding with a band of shallow levels E3 = Ec–0.02–0.15 eV. Three additional bulk traps E2/E5 (Ec–0.8 eV, / Ec–0.17 eV, ) and E4 (Ec–0.23 eV, ) are also found in the regrowth and nonregrowth samples, respectively. Their possible spatial locations and origins are discussed.

The mapping of the current induced by a focused electron beam in a scanning electron microscope (SEM) has been used to localize electrically stressed regions in the AlGaN/GaN-on-Si Schottky barrier diode (SBD) structures cross-sectioned by the focused ion beam (FIB) technique. We have shown that homogeneously distributed electron beam induced current (EBIC) intensity detected below the Schottky contact at 0 V changes with increasing reverse voltage V R and peaks at the edges of a field-plate region. The build-up of local microavalanches at high electric voltages has been indicated by overexposed EBIC signal at areas following the edges of the field plate structure. Interpretation of EBIC measurements is supported by electro-physical modeling and simulations employing the 2-D finite element method in Synopsys TCAD Sentaurus. The simulations prove that the electric field intensity in the SBD locally reaches values sufficiently high to trigger multiplication of the excessive carriers generated by an electron beam, which helps one to visualize and localize critical regions in GaN-based power electronic devices by the EBIC method.

In this paper the reliability of the vertical GaN-on-Si stack for lateral p-GaN HEMTs dedicated to low-voltage applications is discussed in detail by comparing wafers with different buffer thicknesses and growth condition of the AlN nucleation layer. The vertical robustness and the time-dependent vertical breakdown will be investigated in detail, demonstrating that the buffers with reduced thickness are suitable for 100 V applications. Moreover, the voltage drop on the different layers of the vertical stack will be extracted at the breakdown, and a model able to explain the degradation of the vertical stack will be proposed.

In this work, the performance and stability of integrated power Schottky Barrier Diodes (SBD) are reported. We demonstrate the fabrication method to integrate Gated Edge Termination (GET)-SBD into a p-GaN E-mode GaN power technology for 200V power switching applications. The 30mm wide integrated SBDs show a low forward voltage (Vf) and can deliver more than 10A and 6A at Vac=3V for 25°C and 150°C, respectively. Furthermore, an on-resistance (Ron) increase of less than 20% up to 200V at 25°C/150°C can be obtained during pulsed IV characterization and OFF-state stress, indicating a promising stability of the integrated GET-SBDs on power p-GaN Gate High Electron Mobility Transistors (HEMTs) platform.

The growing interest for 5G radios pushes technology development towards low-cost and high-performance solutions for operating at microwave and mm-wave. Downscaling CMOS technology has allowed the integration of high-speed transceivers on silicon chips, but high-power amplifiers rely on III-V technologies to deliver the power and efficiency levels required by modern radios. In this work, we motivate the interest of non-Si technologies to meet 5G requirements, and we explore two routes to enable the fabrication of compound semiconductor devices on a large-scale manufacturable Si platform [1,2]. We provide insight on the potential of these new technologies for the design of advanced front-end modules, including modelling and reliability challenges. In the first route (Figure 1(a)), we report on Al(Ga,In)N HEMTs, MISHEMTs and MOSFETs integrated on 200 mm Si wafers using Au-free processing in standard Si CMOS tools, and discuss the performance trade-offs, limitations and solutions. State-of-the-art contact resistance of 0.14 Ω.mm is demonstrated for a non-Au, low thermal budget (<600 oC) contact scheme, as well as a high vertical breakdown voltage (VBD) of >300 V. We show that MISHEMTs, which feature the highest field effect mobility (μFE), >2000 cm2/V.s, and the best 1/f noise performance, have the potential to outperform the other device types in terms of device scalability for high frequency operation. The GaN-on-Si substrate optimization for low RF losses and nonlinear distortion is further discussed. The second route (Figure 1(b)) includes the formation of HBT on Si wafer by selective epitaxy. We demonstrate GaAs/InGaP HBTs grown on a 300 mm Si substrate. A DC current gain of ~112 and breakdown voltage, BVCBO, of 10 V is achieved. The emitter-base and base-collector diodes show an ideality factor of ~1.2 and ~1.4, respectively. This demonstration shows the potential for enabling a hybrid III-V CMOS/ technology for 5G and mm-wave applications, not limited to GaAs but which can also be extended to InGaAs on a 300 mm Si substrate. Figure 1

This article aims to study the degradation of Schottky Barrier Diodes (SBDs) with a Gated Edge Termination (GET) under ON-state stress conditions. After all the stress experiments a recoverable behavior is observed, which indicates charge trapping in pre-existing defects and no creation of new traps. A broad statistical analysis demonstrates better reliability and a longer lifetime compared to previous works in a 200-V technology. Some systematic differences in parameter degradation are observed depending on wafer location, likely caused by process-related variations. By using matched pairs (MPs) technique, we have demonstrated that probability distributions characterized by single Weibull slopes can be obtained over the wafer that could allow better characterization of the intrinsic reliability of these devices.

With increasing challenges in reducing power density while keeping and even increasing the device performance at every new technology node, innovations in both the device architecture and materials will be needed to ensure continuous improvements in power, performance, area and cost. For the last decade, replacing the Si channel by higher mobility materials like III-V and (Si)Ge has been considered as one of the most challenging innovations needed to further scale down the supply voltage and improve the overall energy efficiency of CMOS circuits. While these materials will not only contribute to enhancing the standard CMOS performance, the possibility of integrating these materials on a Si platform opens exciting new opportunities to build unique circuits, systems and applications. Especially in RF applications, co-integration of III-V/GaN and Si CMOS might be the key enabling technology to provide the speed and power efficiency required for next generation mobile communications. While the device architectures under consideration differ from nowadays ultra-scaled FinFET and nanowire/nanosheet technologies, and their scaling in general is more relaxed, there are significant challenges related to integrating these components on Si substrates. It will need innovations in patterning, deposition and cleaning, next to addressing the challenges of handling these novel materials in a standard CMOS environment. In this work, we will review the status and integration challenges of these materials for both advanced CMOS technologies and RF applications. Focus will be put on the required advancements in etch and deposition needed to enable the integration of these novel materials and devices on a Si platform.

This paper analyses the influence of the GaN and Si3N4 passivation (or “cap”) layer on the top of the AlGaN barrier layer on the performance and reliability of Schottky barrier diodes with a gated edge termination (GET-SBDs). Both GaN cap and Si3N4 cap devices show similar dc characteristics but a higher density of traps at the SiO2/GaN interface or/and an increase of the total dielectric constant in the access region result in higher $R_{\mathrm{ON}}$ -dispersion in GaN cap devices. The leakage current at medium/low temperatures in both types of devices shows two low-voltage-independent activation energies, suggesting thermionic and field-emission processes to be responsible for the conduction. Furthermore, a voltage-dependent activation energy in the high-temperature range occurs from low voltages in the GaN cap devices and limits their breakdown voltage ( ${V}_{\mathsf {BD}}$ ). Time-dependent dielectric breakdown measurements show a tighter distribution in Si3N4 cap devices (Weibull slope $\beta = {3.3}$ ) compared to GaN cap devices ( $\beta = 1.8$ ). Additional measurements in plasma-enhanced atomic layer deposition (PEALD)-Si3N4 capacitors with different cap layers and TCAD simulations show an electric field distribution with a strong peak within the PEALD-Si3N4 dielectric at the GET corner, which could accelerate the formation of a percolation path and provoke the device breakdown in GaN cap SBDs even at low-stress voltages.

We report on Al(Ga,In)N HEMTs, MISHEMTs and MOSFETs integrated on 200 mm Si wafers using Au-free processing in standard Si CMOS tools, and discuss the performance tradeoffs, limitations and solutions. The main highlights of process optimization include low RF transmission loss (0.15 dB/mm at 20 GHz), state-of-the-art contact resistance (R C ) of 0.14 Ω mm for a non-Au, low thermal budget (<600 °C) contact scheme and a high vertical breakdown voltage (V BD ) of >300 V (pre and post device processing). We show that MISHEMTs, which feature the highest field effect mobility (μ FE ), >2000 cm 2 /V.s, and the best 1/f noise performance, have the potential to outperform the other device types in terms of device scalability for high frequency operation.

We report the first comprehensive research about GaN power integrated circuits (ICs) on GaN-on-SOI (silicon-on-insulator). Specific stepped (Al)GaN superlattice buffer and highly robust deep trench isolation are developed. Various components including HEMT, metal-insulator-metal (MIM) capacitor, Schottky barrier diode (SBD), two-dimensional electron gas (2DEG) resistor, and resistor-transistor logic (RTL) are co-integrated, compatible with the p-GaN technology. Based on these achievements, 200 V GaN HEMT with integrated driver shows an extraordinary switching performance. A 48V-to-1V single-stage buck converter is realized using a GaN half-bridge with integrated on-chip drivers. Further, an all-GaN buck converter containing a smart control pulse-width modulation (PWM) circuit, dead-time control, drivers, and half-bridge is successfully designed using the GaN IC platform process design kit (PDK).

This paper analyzes two important reliability issues in AlGaN/GaN devices: positive bias temperature instability (PBTI) and time-dependent dielectric breakdown (TDDB). The summarized results of our previous PBTI studies in MOS-HEMTs show that the threshold voltage degradation in devices with SiO 2 as gate dielectric is characterized by a universal decreasing behavior of the trapping rate parameter and is ascribed to charge trapping in the SiO 2 and at the SiO 2 /GaN interface. On the contrary, the degradation observed in Al 2 O 3 - and AlN/Al 2 O 3 -gate stacks is mainly attributed to charge capture in the pre-existing dielectric traps with a negligible interface state generation. Additionally, the insertion of a thin AlN layer impacts on the device reliability because larger trap density, faster charge trapping, wider trap energy distribution and slower charge release are observed compared with devices without this layer. The dielectric importance of GaN-based devices has been also investigated in Schottky Barrier Diodes (SBDs) with a gated edge termination (GET). Our recent TDDB results indicate a narrower Weibull distribution, and a longer time to failure in devices with a double GET layer structure and with a thick passivation layer (2 GET-THICK) than in single GET devices with a thin passivation (1 GET-THIN). Therefore, the former structure is more suitable for high-power and high-temperature applications.

This paper focuses on the time-dependent breakdown of the AlGaN/GaN Schottky barrier diodes with a gated edge termination (GET) submitted to high-voltage stress. The impact of the GET structure, the passivation layer thickness, and a preclean process (sulfuric acid and hydrogen peroxide mixture + ammonia and hydrogen peroxide mixture) before the GET layer deposition on the time to breakdown t(BD) is analyzed. Initially, a reference structure with a single-GET structure, a thick passivation layer and excellent performance under dc, and pulse characterization is submitted to stress. The results show that the time to failure follows a Weibull distribution with high shape parameter values (beta similar to 3 and/or beta similar to 5) related to intrinsic failure mechanisms. The exponential dependence of tBD on the stress voltage suggests a degradation driven by the electric field, while lower thermal activation energies indicate that temperature acts as a weak acceleration factor. A more uniform distribution of the electric field-by adding an additional peak (double-GET structure) or with more equilibrated peaks (thin passivation structure)-and a more aggressive preclean process before the GET layer deposition improves the breakdown voltage and prolongs the device lifetime.

Technology Computer Aided Design simulations are used to assess the influence of carbon in the back-barrier layers of GaN-on-Si wafers on the voltage distribution in GaN Schottky diodes. It is shown that carbon cannot be present as an acceptor only - as it is commonly assumed. The carbon needs to be compensated by donors or partly electrically inactive in order to explain the observed high hard breakdown voltage in GaN-on-Si Schottky diodes. Furthermore, it is shown that the level of donor compensation of the carbon will have a significant influence on the two-dimensional voltage distribution in the devices, and, hence, on the surface electric field peaks. This conclusion is important to consider in the design of field plate extensions of the Schottky diode.

Enhancement mode 650V rated p-GaN gate HEMTs are fabricated on 200 mm p+ Si substrates by using an industrial, Au-free process. The devices show true e-mode performance, with a high Vt of 2.8 V, low off-state leakage current and are dynamic RDS-ON free over the complete VDS and temperature range. High temperature reverse bias (HTRB) testing is done on-wafer and after packaging. For the first time, 650 V e-mode power HEMTs realized on 200 mm Si substrates, show industry ready device performance and pass 1008 hour reliability testing, at VGS=0 V, VDS=650 V.