A self-purging system is proposed which uses a digital voter that automatically adjusts the threshold of the voter as failed modules are purged. The switch used is no more complex than the switch used by the self-purging redundancy proposed by Losq [6]. However, the system presented here can tolerate single module failures at any given time. This system is useful for applications in which aging or stress is the cause of failure rather than noise.
New quantum electronic devices such as resonant tunnelling diodes and transistors have negative differential resistance characteristics that can be exploited to design novel high-speed circuits. The high intrinsic switching speed of these devices, combined with the novel circuit structures used to implement standard logic functions, leads to ultrafast computing circuits. The new circuit structures presented here provide extremely compact implementations of functions such as carry generation and addition. The most significant impact of these circuits on the field of logic design is the introduction of a totally new set of relative costs of various basic gates; re-evaluation of the logic in the light of these new cost functions leads to ultrafast and compact designs
Integrable nonlinear building blocks such as multipliers, dividers, and piecewise linear approximation circuits using current conveyors are presented. Several practical circuits including an amplitude modulator, a squarer, a square rooter, and nonlinear resistors also have been demonstrated experimentally. The results presented in the paper will facilitate realisations of nonlinear circuits using CCIIs.
Silicon carbide (SiC) is a promising material for semiconductor devices operated at high temperatures because of its large energy bandgap, high thermal conductivity and silicon compatibility. This paper develops an analytical model to predict and compare the d.c and a.c performance of SiC and conventional Si bipolar junction transistors (BJTs) at high temperatures. Based on the device parameters available in the literature, our calculations show that the SiC BJT indeed possesses a higher current gain than its silicon counterpart as the temperature is increased beyond 500 K. This is primarily because SiC has a larger bandgap than Si. As a result, at high temperatures, the majority carrier concentration in the base of the SiC BJT remains the same value as the doping concentration, whereas the majority carrier concentration in the base of the Si BJT increases considerably beyond the doping concentration. The cutoff frequency of the SiC BJT, however, decreases and becomes smaller than that of the Si BJT when the temperature increases. We suggest this is caused by a faster decrease in the electron mobility of SiC than of Si as the temperature is increased. The model compares favourably with data measured from a typical Si BJT.
A new method for modelling, concurrently, the small-signal and the noise performance of active microwave devices is proposed. Here the determination of the element values in a device equivalent circuit is no longer dependent only on the scattering parameters, but also on the device noise parameters. In other words. the device noise performance is treated as an intrinsic set of characteristics of a device like the S-parameters themselves and influences the determination of element values in the device equivalent circuit. On using the concurrent modelling procedure suggested in this paper. it has been found that, not only can the small-signal performance be simulated accurately, but also the prediction of noise performance is in much better agreement with measurements than those of recent published models [1, 2].
A new compound semiconductor complementary transistor technology is proposed and the constituent devices demonstrated in discrete form. The n-channel transistor exhibits a peak transconductance of 110 mS/mm, a drain current density of 24 0 mA/mm and a unity current gain frequency of 9.5 GHz for a nominal gate length of 1 μm. The p-channel transistor has a peak transconductance of 35 mS/mm and a drain current density of 65 mA/mm for an effective gate length of 1.1 μm. Compatibility of this technology with optical devices is shown by fabricating a laser from the same material. Threshold current densities as low as 950 A/cm2 and external efficiencies of 50% are obtained
An algorithm is presented or minimal state-space realisation of recursive and non-recursive three-dimensional systems. This algorithm reduces the problem of minimal realisation to that of solving a linear system of matrix equations. Necessary and sufficient conditions for minimal realisation are estabiished and analytical expressions for the state-space system matrices are derived.
The classical solution to the design of both analogue and digital filters with magnitude and delay constraints is to cascade a minimum phase circuit satisfying the magnitude constraint and an allpass circuit that equalises the delay distortion caused by the first. Such a solution is inefficient and, in this paper, a simple method is considered whose aim is to meet both constraints simultaneously in the digital case. The filter model that is used is a parallel arrangement of allpass circuits which allows a large range of transfer functions to be realised. This model is efficient in the sense that the number of multipliers required equals to the filter order. A sequential quadratic programming technique coupled with a single-line template is used to find the set of coefficients which minimises the squared error. A novel way of setting up the frequency grid is proposed which aims to increase the loss quickly in the transition band. The choice of suitable starting points has an important impact on the length of the optimisation process. A particularly efficacious choice is presented here. Examples are provided illustrating the method, including lowpass, bandpass and multiple bandpass designs, as well as comparing it with a recently reported technique.
A novel high-speed sense amplifier for use with nonvolatile single-transistor memory cells is described. Using a current-sensing scheme and novel circuit techniques, the amplifier achieves sensing speeds equal to or better than those achievable by memory arrays using two transistors per cell. Other circuit techniques were used to improve the circuit-noise immunity as well as sensitivity to critical mask misalignments including the use of output latches, dummy bit lines and decoded odd/even reference-memory-cell selection. The circuit was implemented on a 32 k EPROM memory chip using 1.5 mum N-well CMOS process.
The present investigation deals with the distributed parameter analysis of the p-n junction solar cell in the current-induced case at low level injection. The theory, for the first time, takes into account the metal-semiconductor contact resistance, along with the base bulk resistance and the diffused layer shear resistance. The transcendentally nonlinear differential equations for the emitter layer current and voltage have been solved analytically. Additionally, expressions for the I-V characteristic and equivalent 'lumped' series resistance have been established. Such physical parameters are very useful in the optimisation of the contact finger width and separation. Inclusion of the contact resistance, even for very small values, corresponds to the nonuniform carrier generation within the metallic grid. Therefore, the results are affected both qualitatively and quantitatively. The most important effect has been calculated in the I-V characteristics resulting from an additional contribution to the series resistance. Analysis reveals that the series resistance and the diode quality factor vary with applied current.
The authors propose an optimised design methodology for the double and triple optimised charge pump. The circuits discussed give an output voltage greater than the supply voltage and are commonly used in power IC or memory to allow the switching on of a MOS device. The theoretical models of charge pumps in the transient region are reported to obtain better knowledge of the circuits and the optimised design.
A new realisation of DPCM video signal/image processing is introduced to increase the throughput rate and reduce the hardware cost of the 2D systolic digital filters. This achieved by using a DPCM coding system with a 2D predictor and a 27-level symmetric nonuniform quantiser prior to processing. The advantage of the symmetric nonuniform quantiser is that the size of memory required for multiplication is reduced by a factor of 16 compared to 4 in the existing DPCM implementations. It is shown that the new realisation results in a 64% increase in the throughput rate and a significant reduction in the hardware cost. From the objective and subjective tests carried out, it is shown that the new realisation results in images with visual quality similar to those obtained using conventional processing. Also, the effect of the choice of the 2D predictor is discussed, where it is shown that a 2D predictor with integer coefficients is the most appropriate for DPCM processing
There exists an increasing need in power electronics for efficient three-phase inverters. They can find application in power control of AC motors or as an intermediate stage in DC-DC converters. It seems that employing three-phase oscillators for such inverters can be an appropriate solution. However, for the sake of efficiency and also simplicity, it should be beneficial that the three-phase oscillators will consist of high-Q three-phase resonators. The present paper describes several circuits that can be entitled three-phase resonators. The discussion is mainly related to the topological structures of the systems. A numerical simulation of their dynamics is also given. The three-phase resonators consist of six reactors (three inductors and three capacitors), and not merely of three as might have been expected. This is probably due to the duality existing in electromagnetics. Active elements are added mainly for sustaining the oscillations. However, a further task for them is to assist in balancing the three-phase system. Some of the models are advantageous since they have in inherent property to constrain the DC bias in the three-phase variables, both in the currents and in the voltages, to zero.
Using Rabbani's model for generation width, a differential equation, which describes the capacitance-time (C-t) transient characteristics of pulsed MOS capacitors was obtained. The theoretical (C-t) transient characteristics can be obtained by integrating this differential equation. It has also been shown that the minority generation lifetime of semiconductors can be determined by matching an experimental (C-t) transient characteristic with the theoretical one
Some current-voltage characteristics of GaAs MESFET at elevated temperatures have been measured and the existence of zero temperature coefficient (ZTC) points in the drain current of DFETs and EFETs are presented. At these points of operation, with a specific value of gate bias, the device drain current characteristics are stable in temperature. The ZTC point for the saturation region of operation is presented for both types of devices, whereas for the linear region of operation the ZTC point is reached only with DFET. The existence of the ZTC point is shown to depend critically on the flow of leakage currents. The ZTC points are analysed with an analytical model that is capable of estimating the corresponding drain current and gate bias values. In addition, an analytical model for the threshold voltage and transconductance parameter is discussed by starting from device physical and geometrical parameters for finding the ZTC point. The analytically solved results are shown to correspond closely to the experimental results
I(DDQ) testing has been shown to be an efficient way to test CMOS technology circuits when realistic failures, bridges among others, are considered. A particular group of bridging faults cause the circuit to oscillate because of unstable feedback. This paper focuses on the evaluation of I(DDQ) testability for these bridging faults. An electrical circuit model allows the analytic derivation of characteristics of the oscillating I(DD) behaviour. It is shown that oscillating faults are testable by classical I(DDQ) sensors. The knowledge of the ripple frequency and the maximum and minimum values of the oscillating I(DD) current allows the characterisation of the I(DDQ) levels, and it is useful in the design or choice of a current sensor in the general case.
The perpendicular transport properties of a p-GaAs/delta-doped superlattice/n+-GaAs structure were studied at 300 and 77 K. An interesting S-shaped negative differential resistance (NDR), resulting mainly from avalanche multiplications within the superlattice region, was observed at 300 K. A different multistate NDR phenomenon and an interesting hysteresis behaviour were found at 77 K. The multistate NDR is attributed to a sequential subavalanche multiplication process occurring within superlattice periods; holes created by avalanche multiplications play an important role in the transport properties. The hysteresis behaviour at 77 K seems to be caused by the heavily accumulated holes, which cannot react synchronously with the applied electric field.
It is shown that to simultaneously achieve requirements of dynamic (storage time) and static (on-resistance, peak drain current) power transistor characteristics, an irradiation/anneal processing cycle may be used. This includes annealing at a temperature range limited by the thermal stabilities of the A-centres and divacancies (i.e. 300-380-degrees-C). The irradiation flux by high energy electrons is chosen to accumulate the preassigned concentration of A-centres in the epilayer where transistors have been formed. This condition drives the choice towards high flux irradiation (fluxes above 10(16) cm-2) for power transistors. In addition, the irradiation/annealing process imposes constraints on impurity concentrations in the heavily doped drain (or collector) region and in the epilayer. The shallow donor impurity concentration must greatly exceed the oxygen concentration in the heavily doped region and the oxygen concentration must greatly exceed the carbon concentration in the epilayer.
A new method for high speed realisation of 1-dimensional (1D) linear phase FIR digital filter is presented. The method makes use of pipelining in systolic arrays to reduce the minimum clock cycle time, the delayed two-path structure to increase processing speed, and the symmetry of coefficients in a linear phase FIR digital filter to reduce multiplications. The resultant systolic delayed two-path digital filter structure is consisted of four systolic arrays built from one type of basic cells with nearest neighbour interconnections. The method is optimal in terms of the number of multiplications. Both input and output of the proposed filter structure can also be systolised to form an overall pure systolic structure. The proposed digital filter structure can provide a speed improvement of 32 times as compared to that of a direct realisation of the same filter using a single processor. The proposed method is attractive for high speed adaptive and nonadaptive digital filtering
The CAD of a complex multielectrode arrangement for flow imaging is explored using the finite element method (FEM). This electrode arrangement forms the primary sensor subsystem for an electrical capacitive tomography (ECT) system. Results are presented in the form of sensor's performance parameters as functions of its various geometric parameters. The performance parameters include the standing and normalised capacitances, ratio of the maximum to minimum capacitance of the sensor (Kc) and the sensor's spatial sensitivity distributions. Extensive computer simulation studies were undertaken in calculating these parameters, and the techniques in finite element (FE) model definition, mesh generation and refinement, error minimisation and checking are highlighted in the paper in relation to the effective and efficient use of the FEM. Detailed results for a particular sensor design are compared with an experimental prototype and found to give good agreement. The response of the sensor to various flow regimes is also presented and analysed to optimise its performance for image reconstruction.
