Motivation plays a key role in effective learning but motivation needs to be sustained through feedback responses, reflection, and active involvement in order for learning to take place. This work focuses on incorporating active methods of teaching such as game-based learning and simulation-based learning. Game theme-based instructional (GTI) modules produce better results than traditional learning techniques because it increases motivation and engagement of students as they learn interactively. This work is aimed at assessing the motivation and engagement of undergraduate students for GTI modules in introductory data structure courses. This paper discusses the design, implementation, and evaluation of a GTI module to teach the linked list and binary tree data structure. For the design and development of GTI modules, we have incorporated FDF (four-dimensional framework) and constructive approach for learning. The GTI modules were evaluated based on the five components of the Science Motivation Questionnaire II (SMQII). We have also performed an ANOVA test for evaluating the motivation based on familiarity with other virtual reality games and the t-test for evaluating the motivation of students when they use GTI modules as a learning tool. The results of the evaluation of GTI modules shows that instructional modules can efficiently promote learning by encouraging the students’ participation.
The use of virtualized systems is growing, and one would like to benefit from this kind of systems also for real-time applications with hard deadlines. There are two le ...
As microprocessor performance grows, high throughput and the power management are becoming more important on embedded real-time systems. RealTime Voltage and Frequency Scaling (RT-VFS) has been proposed to reduce the power consumption and ensure real-time constraints. An imprecise computation model adds an optional part to Liu and Layland’s model to improve the quality of computations. This paper proposes the scheme to integrate an imprecise computation model and RT-VFS that can reduce the power consumption and improve the quality of computations within real-time constraints. Moreover, we implement this scheme on Dependable Responsive Multithreaded Processor (D-RMTP). D-RMTP is a prioritized simultaneous multithreaded processor for embedded real-time systems and D-RMTP system in a package supports RT-VFS. We implement the proposed scheme by use of D-RMTP original features to improve the quality of computations and reduce the energy consumption. Through experimental evaluation, we show that the proposed scheme satisfies both the lower energy consumption and higher performance on real environments. In our evaluation, the proposed scheme achieves a maximum of 135% improvement of the quality of computations per energy consumption. keywords: Embedded Real-Time System, Power Consumption, RT-VFS, and Imprecise Computation Model
Real-time systems such as humanoid robots require low jitter and high Quality of Service (QoS). An imprecise computation is one of the solutions to improve QoS but dynamic-priority imprecise real-time scheduling has high jitter. Semi-fixed-priority scheduling was presented to achieve low jitter and high QoS for imprecise computation. Unfortunately, a semi-fixed-priority scheduling algorithm, called Rate Monotonic with Wind-up Part (RMWP), has high jitter if the actual case execution time (ACET) of each task is shorter than its worst case execution time (WCET). We propose a new semi-fixed-priority scheduling algorithm, called Rate Monotonic with Wind-up Part++ (RMWP++), to achieve the zero-jitter of each task with harmonic periodic task sets. The zero-jitter technique adds the previous and post optional parts to the extended imprecise computation model that has a second mandatory (wind-up) part. We prove that the jitter of each task in RMWP++ is always zero and the least upper bound of RMWP++ is one with harmonic periodic task sets on uniprocessors. Simulation results show that RMWP++ achieves the zero-jitter and has a smaller number of context switches than RMWP, if the ACET of each task is shorter than its WCET.
Parallel counters have been studied for several decades as a component in high speed multipliers and multi-operand adder circuits. Using a generator polynomial as a formalism for describing parallel counters in the general case, parallel counter properties can be derived and inferred. Furthermore, the structure and decomposition of the generator polynomial can suggest different implementation strategies. These include simple implementations of (7,3) and (15,4) parallel counters. By grouping factors, the design of a fast (7,3) parallel counter is presented. Finally, the generator polynomial is extended to permit factors of different weights. This extension provides a means for describing the design of the (5,5,4) and (4,5,5,5) multicolumn parallel counters.
A new collision detection algorithm is presented that solves the all-pairs collision detection problem using parallel processing. The design of the algorithm is based on a linear octree and runs in parallel with a theoretical performance of O((n log n)=k) run time. The algorithm has been implemented as a collision detection system using object-oriented design techniques and a client-server architecture. The architecture of the collision detection system is designed to use the parallel capabilities of both shared-memory, multi-processor computers and clusters of networked computers. Additionally, the modularity of the collision detection system gives application developers the flexibility to choose the level at which the collision detection system is integrated into an application. Using the collision detection system, experimental results have been generated that demonstrate how the algorithm performs according to the calculated theoretical performance.
