This paper presents a comprehensive comparison of algorithmic-level design approaches for implementing unified multiplier hardware tailored for Falcon—an emerging post-quantum digital signature standard. A key requirement for Falcon is a 64-bit multiplier with a throughput of one multiplication per cycle that supports floating-point operations. While several multiplication techniques exist, their suitability depends on bit size, target technology, throughput, energy, and latency requirements. Our key novelty lies in conducting, for the first time, a systematic analysis and comparison of these techniques specifically for Falcon’s multiplier needs across both FPGA (Virtex-7 Series Xilinx) and ASIC (SkyWater 130nm node) platforms. We evaluate four approaches: a baseline design without optimizations, an asymmetric Tiling approach optimized for FPGA multiplier block utilization, Comba, and the Karatsuba algorithm. Surprisingly, on FPGAs, Karatsuba achieves the highest area efficiency (19.2
The use of JSON Web Token (JWT)s has become ubiquitous in the Internet of Things (IoT) for the secure exchange of messages between the things and the Cloud. However, the standard that describes the JWT is fragmented, and interpretations may pave the way for abuses. In this work we show a supply chain attack that exploits a weakness in the JWT standard. In particular an attacker that takes control of one device during production, may be able to create a series of valid JWTs, that may be used further after the deployment, to impersonate the device when accessing the Cloud infrastructure. Among the advantages of the attack is that the network is completely unaware about the JWTs created in the supply chain by the attacker. We show that the use of JWTs in the context of the Google Cloud IoT Core [15] infrastructure paves the way for a subtle attack, and that quite unexpectedly, the presence of an Secure Element (SE) on the connecting device does not allow to thwart the problem, but instead seems to make a solution harder to reach. We showcase our attack on the - now retired - Google Cloud IoT Core, in order to avoid malicious use of our findings, but our discovery can be applied to other services that provide token-based authentication. For example we further show that the same weaknesses applies to other tokens like the Concise Binary Object Representation Web Token (CWT) and the Entity Attestation Token (EAT) [23, 26], and to platforms like HiveMQ and EMQX [13, 17] providing a much wider attacker scope then merely a single token type or Cloud provider. Furthermore, our attack also applies to the Open Charge Metering Format (OCMF) standard, used for recording meter readings from charging station for Electric Vehicles (EV) [33]. In order to thwart the presented attack we provide a few countermeasures that can be applied, depending on the IoT infrastructure at hand.
This work introduces DEFIv2 - an efficient hash-and-sign digital signature scheme based on isotropic quadratic forms over a commutative ring of characteristic 0 . The form is public, but the construction is a trapdoor that depends on the scheme’s private key. For polynomial rings over integers and rings of integers of algebraic number fields, the cryptanalysis is reducible to solving a quadratic Diophantine equation over the ring or, equivalently, to solving a system of quadratic Diophantine equations over rational integers. It is still an open problem whether quantum computers will have any advantage in solving Diophantine problems.
FrodoKEM is a Post-Quantum (PQ) Key Encapsulation Mechanism (KEM) built on the Learning with Errors (LWE) problem. Unlike other lattice-based approaches, it avoids using structured lattices to enhance its resilience against attacks. FrodoKEM is selected as a Round 3 alternate candidate in the US National Institute of Standards and Technology (NIST) Post-Quantum Cryptography (PQC) Standardization competition, recommended/accepted by several information security agencies in the world, and currently being reviewed for adoption by the International Organization for Standardization (ISO), which calls for efficient real-world implementations of the algorithm. This paper introduces an optimized Field Programmable Gate Array (FPGA)-based architecture for FrodoKEM that achieves up to a factor of 3.5 reduction in resource utilization compared to existing studies, eliminates the need for Digital Signal Processing (DSP) blocks in FPGA implementations, reduces the number of required BRAMs, and delivers up to 9.7 times the throughput. The architecture benefits from parallelization, which results in faster performance, and it integrates key generation, encapsulation, and decapsulation into a single unified implementation that supports all three parameter sets; FrodoKEM-640, FrodoKEM-976, and FrodoKEM-1344.
In this paper, we present a simple meet-in-the-middle attack that requires low data and memory resources. To evaluate the complexity of the attack, we also propose an automated tool that calculates the time, data, and memory complexities based on the suggested matching points. Our method operates at the bit level and employs a known-plaintext attack, with no constraints on the attacker’s choice of data. We apply our tool on various lightweight block ciphers, including CRAFT, Midori, WARP, PRESENT, and ARADI. For CRAFT, our tool successfully identified an attack targeting 15 rounds using 3 known plaintexts. In the case of Midori64 and Midori128, the tool proposed attacks on 5 rounds with 16 known plaintexts and 7 rounds with 3 known plaintexts, respectively. For WARP, the tool discovered an attack on 18 rounds utilizing 7 known plaintexts. Additionally, for PRESENT80, the tool identified an attack on 6 rounds with 18 known plaintexts, and for ARADI, an attack on 5 rounds with 28 known plaintexts was determined.
This paper presents an enhancement to cube-attack-like cryptanalysis by minimizing output-bit dependency on related key bits, thereby improving attack complexity. We construct two distinct initial states differing exclusively in predetermined bit positions. Through independent cube summation and state difference analysis, we observed reduced related key bits dependency for specific output bits. We validate our approach by targeting three Keccak keyed variants Ketje Minor, Keccak-MAC-512 and Keccak-MAC-384, developing a dedicated tool to recover all output-bit superpolies. Using our computational resources, we successfully attacked 4-round of Ketje Minor and 5-round of other variants, confirming both the method’s validity and practical applicability. While the best known attacks on these structures reach 7-round, our results improve upon the 5-round. We construct our initial state configurations based on the automated method proposed by Bi et al. in Design, Codes and Cryptography (2019), and compare our results with theirs. For the 4-round Ketje Minor, we reduce the time complexity from 2^20 to 2^16.8 ; for 5 round Keccak-MAC-512, from 2^34 to 2^31.2 ; and for 5 round Keccak-MAC-384, from 2^27.6 to 2^26.5 .
In this work, we present the first independent security analysis of DIZY, a recently proposed ultra-lightweight stream cipher with two variants: DIZY-80 and DIZY-128. Our analysis focuses on DIZY’s resistance to linear and differential cryptanalysis. We employ a formal technique known as Mixed Integer Linear Programming (MILP), which enables us to model the internal structure of DIZY and search for characteristics that describe how XOR differences or linear masks propagate through the cipher. Specifically, we construct such characteristics to evaluate how many S-boxes become “active” during keystream generation, as this number directly affects the cipher’s resistance to these attacks. Contrary to the designers’ claim that any linear or differential characteristic over 8 rounds must involve at least 20 active S-boxes in DIZY-80 and 22 in DIZY-128, we identify characteristics with only 18 differentially or linearly active S-boxes and 20 linearly active S-boxes, respectively. We mount two distinguishing attacks on each cipher. Our 3-round linear distinguishing attack requires 2^23 bits of keystream, while the 4-round version requires 2^35 bits for DIZY-128 and DIZY-80, respectively. Our 2-round differential resynchronization attacks succeed using only the first four bytes of keystream data from approximately 2^30 and 2^26 different initializations with chosen initialization vectors (IVs) for DIZY-128 and DIZY-80, respectively. While these attacks do not compromise the full 15-round version of the cipher, they provide valuable insights into the design of DIZY and contribute to a deeper understanding of the security requirements of its diffusion layer.
The Number Theoretic Transform (NTT) is a foundation of Module-Lattice-Based Cryptography (MLBC), yet its implementation can be resource-intensive, posing challenges for deployment on low-power and constrained devices. This paper introduces LightNTT, a high-efficiency NTT/iNTT core specifically architected for ML-DSA, emphasizing minimal resource utilization and optimal performance. LightNTT leverages a constant-geometry dataflow combined with a deeply pipelined single butterfly unit and an optimized Barrett modular multiplier to achieve a compact footprint. Implemented on an Artix-7 FPGA, the design consumes only 590 LUTs, 158 FFs, 2 DSPs, and 2.5 BRAMs. It computes a full 256-point NTT/iNTT in 1056 clock cycles, achieving a latency of 3.49μs at a clock frequency of 300 MHz. Critically, LightNTT demonstrates a superior Area-Time Product (ATP) of 5.82, which is approximately 29
In this paper, we present a comprehensive analysis of various modular multiplication methods for Number Theoretic Transform (NTT) on FPGA. NTT is a critical and time-intensive component of Fully Homomorphic Encryption (FHE) applications while modular multiplication consumes a significant portion of the design resources in an NTT implementation. We study the existing modular reduction approaches from the literature, and implement particular methods on FPGA. Specifically Word-Level Montgomery (WLM) for NTT friendly primes [20] and K ^2 RED [4]. For improvements, we explore the trade-offs between the number of available primes in special forms and hardware cost of the reduction methods. We develop a DSP multiplication-optimized version of WLM, which we call WLM-Mixed. We also introduce a subclass of Proth primes, referred to as Proth-l primes, characterized by a low and fixed signed Hamming Weight. This special class of primes allows us to design multiplication-free shift-add versions of K ^2 RED and naive Montgomery reduction [21], referred to as K ^2 RED-Shift and Montgomery-Shift. We provide in-depth evaluations of these five reduction methods in an NTT architecture on FPGA. Our results indicate that WLM-Mixed is highly resource-efficient, utilizing only 3 DSP multiplications for 64-bit coefficient moduli. On the other hand, K ^2 RED-Shift and Montgomery-Shift offer DSP-free alternatives, which can be beneficial in specific scenarios.
The adoption of NIST’s post-quantum cryptographic standards has accelerated the shift toward quantum-resistant systems. While many protocols like TLS, IKEv2, and Signal can integrate these standards, others still rely on primitives lacking efficient post-quantum replacements. One such primitive is the BLS signature scheme, widely used in proof-of-stake (PoS) blockchains for its ability to aggregate multiple signatures into a single compact one, reducing communication and verification overhead. Recent research has proposed post-quantum aggregate signatures to replace BLS, but existing schemes remain impractical due to high memory usage and slow aggregation. While prior solutions produce smaller signatures (hundreds of KB), they require hundreds of gigabytes of RAM to aggregate 2^10 signatures. In contrast, our scheme generates slightly larger signatures (2–3 MB) but drastically reduces aggregation time and can handle up to 2^16 signatures on a standard laptop, making it significantly more practical. In addition to improved scalability, our design is grounded in strong security principles, relying on minimal assumptions—specifically, the use of secure hash functions. For the signature primitive, we employ XMSS, a stateful hash-based signature scheme that is already standardized by NIST. To the best of our knowledge, no previous post-quantum aggregation schemes have implemented multi-level aggregation. We have implemented this capability, enabling incremental aggregation of signatures across the network. This is particularly relevant to Ethereum’s Beam chain roadmap, which emphasizes modular zk-rollup architectures and the integration of post-quantum primitives. Moreover, by enabling multi-level signature aggregation, our approach provides a practical solution for secure validator coordination and signature verification in future post-quantum Ethereum consensus mechanisms.
We investigate the risk of embedding stealthy hardware Trojans in implementations of multivariate quadratic (MQ) based post-quantum signature schemes that use the Keccak-based hashing module. Our study reveals that MAYO and UOV are more vulnerable due to the predictable interaction of message and secret seed within the Keccak module, while SNOVA and QR-UOV exhibit inherent resilience by deviating from this structure. We demonstrate how minimal hardware Trojans, occupying merely 0.03
Linear Legendre pseudorandom functions were introduced in 1988 by Damgård, and higher degree generalizations were introduced by Russell and Shparlinski in 2004. To the best of our knowledge, there exists no efficient hardware circuit that accelerates the computation of the Legendre PRF in hardware. In this work, we try to address the issue of constructing a hardware accelerator for this task. We show that the most challenging part of constructing such a circuit is computing a sub-circuit that computes the modular reduction p a , when both operands a, p are variable. We propose two ideas for solving this problem. The first uses a number from the equivalence class a p which is easier to compute than the modular reduction itself. We show that this circuit also computes the Legendre symbol correctly, but takes few additional clock cycles to do so. The second uses a sequential circuit for constructing modular reduction, for which we can additionally upper bound the number of clock cycles it takes to finish the computation. We verify our algorithm by synthesizing both circuits using three different standard cell libraries.
The growing integration of embedded cryptographic systems in smart city infrastructure, from connected traffic sensors to smart grids, has heightened the threat of stealthy Hardware Trojans. Lightweight block ciphers, favored for efficiency in such resource-constrained devices, remain susceptible to malicious modification during early design stages. This paper explores Register Transfer Level (RTL)-level Hardware Trojan design and detection through the insertion of nine lightweight Trojans into a Field Programmable Gate Array (FPGA) implementation of the PRESENT lightweight block cipher. The Trojans employ diverse triggering mechanisms based on internal and external system conditions, with payloads ranging from data corruption and information leakage to Denial of Service (DoS) attacks. A Functional Analysis (FA)-based detection method is applied using pseudorandom inputs at the logic simulation level, treating the system as a black-box. Results show that even RTL Trojans with very low triggering probabilities can be detected, albeit with increased simulation time. Hardware overhead remains minimal, with Look-Up Table (LUT) usage rising by just 0.24
Whether stemming from malicious intent or natural occurrences, faults and errors can significantly undermine the reliability of lightweight architectures. In response to this challenge, fault detection plays a pivotal role in ensuring the secure deployment of cryptosystems. Even when a cryptosystem boasts mathematical security, its practical implementation may remain susceptible to exploitation through side-channel attacks. In this paper, we propose a lightweight fault detection architecture tailored for modular exponentiation, a building block of numerous cryptographic applications spanning from classical cryptography to post-quantum cryptography (PQC). Based on our simulations on ARM Cortex-A72 processor, our approach achieves an error detection ratio close to 100
In deep learning side-channel analysis, a neural network is employed to develop a profile of our target device. Data from a similar dummy device is used to construct the profile. However, when the profiling device differs from the target device, the profile may not be accurate enough for a successful attack. This study examines the effect of manufacturing-induced inter-device discrepancies across 14 identical 32-bit STM32F303 devices. To map the manufacturing discrepancies for these devices, we create a tool called MIDSCAN - Manufacturing-Induced Discrepancies SCAN. Our analysis revealed that the 14 ChipWhisperer 32-bit devices have limited manufacturing discrepancies. Only in a multilayer perceptron setup, the manufacturing discrepancies between the profiling and target devices affected the attack performance. In this case, devices that showed more discrepancies based on correlation and difference than the profiling device need additional traces for a successful attack. Manufacturing discrepancies between profiling and attack devices do not affect attack performance for convolutional neural network architectures. No additional attack traces were needed to perform a successful attack. Our findings indicate that statistical metrics, as implemented by MIDSCAN, can estimate inter-device discrepancies for identical devices. Finally, we found that manufacturing discrepancies are limited for 32-bit STM32F303 ChipWhisperer targets, eliminating the need for additional measures for cross-device deep learning attacks.
As embedded systems become increasingly pervasive, ensuring cryptographic security against side-channel attacks has emerged as a critical challenge. While masking schemes are a well-established countermeasure, micro-architectural features inherent to modern processors can introduce unintended leakages that fall outside the scope of classical leakage models. This work presents a first-order masked software implementation of AES-128, including the key schedule, targeting the ARM Cortex-M4 platform. The design adheres to software-specific threshold implementation principles, enforcing horizontal and vertical non-completeness as well as register-uniform masking. A bitsliced representation is adopted, with each share computed at a distinct index and cross-products evaluated independently to preserve security guarantees. The AES S-box is decomposed using a tower field representation, limiting the need to secure only 2- and 4-bit multiplications. Secure Toffoli gate constructions are employed to ensure that cross-domain multiplications adhere to TI constraints. The “changing of the guards” principle is applied to enable randomness reuse, thereby reducing the demand for fresh randomness. In contrast to prior work that prioritizes performance, this research emphasizes real-world side-channel security, validated through extensive practical evaluation using a Test Vector Leakage Assessment. The results demonstrate that secure software implementations are feasible without hardware changes, though this comes with associated performance trade-offs.
Maximum distance separable (MDS) matrices are the main building blocks that provide the maximum possible diffusion in several block ciphers and cryptographic hash functions. In addition to using MDS matrices directly, there are also some indirect but simple and efficient methods that provide the maximum possible diffusion property. In particular, the subfield construction introduced by Barreto et al. in [DCC 56 (2–3) 141–162 (2010)] and its generalization examined by Otal in [IJISS 11 (2) 1–11 (2022)] make use of MDS matrices over smaller finite fields to provide the maximum possible diffusion property over larger finite fields. ZK-friendly hash functions, in contrast to the classical cryptographic hash functions, use higher-dimensional MDS matrices over larger finite fields. In this paper, we examine the applicability of the generalized subfield construction and the possibility of improvements on ZK-friendly hash functions. As a case study, we focus on a recent ZK-friendly hash function Vision Mark-32 presented by Ashur et al. in [IACR Preprint 2024/633]. In particular, instead of using a 24× 24 MDS matrix over 𝔽_2^32 for a 24× 1 column input over {0,1}^32 , we suggest separating the 24× 1 column input over {0,1}^32 into four 24× 1 subcolumns over {0,1}^8 and then using a 24× 24 MDS matrix over 𝔽_2^8 for each subcolumn. This method still keeps the maximum diffusion property without any compromise and provides simplicity and efficiency. For example, it is possible to significantly decrease the required LUT values to 265 from about 9200 and FF values to 102 from about 4600 for the hardware implementation. We also highlight that we do not need any additional tricks such as NTT for field multiplications. We also push the theoretical boundaries of the generalized subfield construction to see how much small finite fields we can use, examine the arithmetization complexity, and discuss its applicability to other ZK-friendly hash functions.
Side-channel attacks pose a serious risk to cryptographic implementations, particularly in embedded systems. While current methods, such as test vector leakage assessment (TVLA), can identify leakage points, they do not provide insights into their root causes. We propose , an architecture-level tool designed to perform side-channel analysis and root cause identification for software cryptographic implementations on RISC-V processors. has two main components: (1) Side-Channel Analysis to identify leakage using TVLA and its variants, and (2) Data Flow Analysis to track intermediate values across instructions, explaining observed leaks. Taking the binary file of the target implementation as input, generates interactive visualizations and a detailed report highlighting execution statistics, leakage points, and their causes. It is the first architecture-level tool tailored for the RISC-V architecture to guide the implementation of cryptographic algorithms resistant to power side-channel attacks. is algorithm-agnostic, supports pre-silicon analysis for both high-level and assembly code, and enables efficient root cause identification. We demonstrate ’s effectiveness through case studies on unprotected and protected AES and unprotected Ascon implementations, where it accurately traces the source of side-channel leaks. We report previously undocumented vulnerabilities due to architectural register usage in the ShiftRows operation of the protected AES implementation. For the Ascon implementation, we report leaks both in the substitution layer and in the diffusion layer, thus reflecting its susceptibility to data-dependent side-channel leakage.
This paper presents a comprehensive comparison of algorithmic-level design approaches for implementing unified multiplier hardware tailored for FALCON an emerging post-quantum digital signature standard. A key requirement for FALCON is a 64-bit multiplier with a throughput of one multiplication per cycle that supports floating-point operations. While several multiplication techniques exist, their suitability depends on bit size, target technology, throughput, energy, and latency requirements. Our key novelty lies in conducting, for the first time, a systematic analysis and comparison of these techniques specifically for FALCON'S multiplier needs across both FPGA (Virtex-7 Series Xilinx) and ASIC (SkyWater 130nm node) platforms. We evaluate four approaches: a baseline design without optimizations, an asymmetric Tiling approach optimized for FPGA multiplier block utilization, Comba, and the Karatsuba algorithm. Surprisingly, on FPGAs, Karatsuba achieves the highest area efficiency (19.2% smaller than the baseline) despite pipelining and more operations, while Tiling outperforms in energy efficiency (35.9% improvement). For ASICs, Karatsuba remains the most area-efficient, but Comba exhibits unexpected energy efficiency advantages (51.5% better than Karatsuba and 22.8% better than baseline). These findings represent the first direct comparison of these techniques under these conditions, providing designers with actionable insights for optimizing FALCON hardware for specific applications and technologies.
In this paper, we focus on the design of a novel authentication protocol that preserves the privacy of embedded devices. A Physically Unclonable Function (PUF) generates challenge-response pairs that form the source of authenticity between a server and multiple devices. We rely on Authenticated Encryption (AE) for confidentiality, integrity and authenticity of the messages. A challenge updating mechanism combined with an authenticate-before-identify strategy is used to provide privacy. The major advantage of the proposed method is that no shared secrets need to be stored into the device’s non-volatile memory. We design a protocol that supports server authenticity, device authenticity, device privacy, and memory disclosure. Following, we prove that the protocol is secure, and forward and backward privacy-preserving via game transformations. Moreover, a proof of concept is presented that uses a 3-1 Double Arbiter PUF, a concatenation of repetition and BCH error-correcting codes, and the AE-scheme Ketje. We show that our device implementation utilizes 8,305 LUTs on a 28 nm Xilinx Zynq XC7Z020 System on Chip (SoC) and takes only 0.63 ms to perform an authentication operation.
