Neuromorphic computing mimics brain-inspired mechanisms through spiking neurons and energy-efficient processing, offering a pathway to efficient in-memory computing (IMC). However, these advancements raise critical security and privacy concerns. As the adoption of bio-inspired architectures and memristive devices increases, so does the urgency to assess the vulnerability of these emerging technologies to hardware and software attacks. Emerging architectures introduce new attack surfaces, particularly due to asynchronous, event-driven processing and stochastic device behavior. The integration of memristors into neuromorphic hardware and software implementations in spiking neural networks offers diverse possibilities for advanced computing architectures, including their role in security-aware applications. This survey systematically analyzes the security landscape of neuromorphic systems, covering attack methodologies, side-channel vulnerabilities, and countermeasures. We focus on both hardware and software concerns relevant to spiking neural networks (SNNs) and hardware primitives, such as Physical Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) for cryptographic and secure computation applications. We approach this analysis from diverse perspectives, from attack methodologies to countermeasure strategies that integrate efficiency and protection in brain-inspired hardware. This review not only maps the current landscape of security threats but provides a foundation for developing secure and trustworthy neuromorphic architectures.

Designing hardware circuits resistant to side-channel attacks increasingly relies on simulation to predict device leakage before fabrication. Current functional verification simulators are designed for extended correctness-checking runs and are ill-suited for producing large numbers of short trace collections with slight input variants needed for side-channel analysis. We present Vogls: an open-source Verilog simulator built for side-channel analysis, that is the first simulator to combine compiled-code performance, full-timing simulation, and fine-grained control over the simulation state. Vogls simulates a timing annotated gate-level AES design 5.9 times faster than Icarus Verilog and is only 30

Edge neural network implementations can be substantially accelerated on FPGAs. Open-source tools like FINN enable real-world deployment of applications in various domains. However, the privacy and security of FPGA-based edge neural network implementations have often been overlooked. Semantic leakage, a new type of side-channel vulnerability, has been identified in both software and hardware neural network implementations.In this paper, we provide an initial analysis of FPGA implementations of convolutional neural networks (CNNs) generated using the open-source FINN framework. Our work follows the recent semantic-leakage threat model, in which the adversary aims to differentiate between categories of input data based on side-channel leakage. We mount a side-channel attack on CNNs compiled with FINN for AMD ZCU104 FPGA and show that FINN-generated designs exhibit such leakage. To further explore how leakage varies, we tune various implementation aspects, including storage elements, arithmetic operations in computation elements, and folding. Our experiments demonstrate that implementing the arithmetic operations and storage elements using look-up tables (LUTs) may be less vulnerable to semantic leakage than using the specific-purpose FPGA blocks. More importantly, we show that more folding transformations enhance resistance against semantic leakage.

The multi-million dollar investment required for modern machine learning (ML) has made large ML models a prime target for theft. In response, the field of model stealing has emerged. Attacks based on physical side-channel information have shown that DNN model extraction is feasible, even on CUDA Cores in a GPU. For the first time, our work demonstrates parameter extraction on the specialized GPU's Tensor Core units, most commonly used GPU units nowadays due to their superior performance, via near-field physical side-channel attacks. Previous work targeted only the general-purpose CUDA Cores in the GPU, the functional units that have been part of the GPU since its inception. Our method is tailored to the GPU architecture to accurately estimate energy consumption and derive efficient attacks via Correlation Power Analysis (CPA). Furthermore, we provide an exploratory analysis of hyperparameter and weight leakage from LLMs in far field and demonstrate that the GPU's electromagnetic radiation leaks even 100\,cm away through a glass obstacle.

Voltage fault injection (VFI) is a hardware-level exploitation technique in which a precisely timed disturbance is introduced to a device’s power supply to induce computational faults. These deliberately injected faults can bypass critical security mechanisms or expose sensitive information. Conventional hardware-based countermeasures, including power-filtering circuits and voltage supervisors, often rely on static detection thresholds and can be circumvented by advanced glitching tools capable of generating perturbations too brief for fixed-trip circuits to detect. This paper presents a Convolutional Neural Network (CNN)-based framework for adaptive detection of voltage glitch attacks. Our method builds on the principle that the system clock signal, which governs processor timing, provides a more sensitive and persistent indicator of glitch-induced perturbations than the compromised power rail. We perform a thorough VFI evaluation, characterizing a wide range of glitch parameters against an AES-128 encryption routine executed on an STM32F410 microcontroller. We delineate the exploitable region of the glitch parameter space using a Support Vector Machine (SVM), thereby avoiding reliance on arbitrary estimations to delimitate exploitable behavior. The resulting exploitable parameter ranges are labeled within the dataset as exploitable and safe executions, which are then used to train the CNN. The resulting model is a CNN classifier that accurately detects exploitable glitch propagation, achieving 98.6% accuracy. The results demonstrate that this approach is well suited for adaptive and resilient hardware security primitives and for mitigating next-generation glitch attacks.

Side-channel attacks pose a serious risk to cryptographic implementations, particularly in embedded systems. While current methods, such as test vector leakage assessment (TVLA), can identify leakage points, they do not provide insights into their root causes. We propose , an architecture-level tool designed to perform side-channel analysis and root cause identification for software cryptographic implementations on RISC-V processors. has two main components: (1) Side-Channel Analysis to identify leakage using TVLA and its variants, and (2) Data Flow Analysis to track intermediate values across instructions, explaining observed leaks. Taking the binary file of the target implementation as input, generates interactive visualizations and a detailed report highlighting execution statistics, leakage points, and their causes. It is the first architecture-level tool tailored for the RISC-V architecture to guide the implementation of cryptographic algorithms resistant to power side-channel attacks. is algorithm-agnostic, supports pre-silicon analysis for both high-level and assembly code, and enables efficient root cause identification. We demonstrate ’s effectiveness through case studies on unprotected and protected AES and unprotected Ascon implementations, where it accurately traces the source of side-channel leaks. We report previously undocumented vulnerabilities due to architectural register usage in the ShiftRows operation of the protected AES implementation. For the Ascon implementation, we report leaks both in the substitution layer and in the diffusion layer, thus reflecting its susceptibility to data-dependent side-channel leakage.

We present the first unified hardware implementation of the post-quantum schemes Module-Lattice-Based Digital Signature Algorithm (ML-DSA) and Module-Lattice-Based Key Encapsulation Mechanism (ML-KEM) protected against side-channel attacks using first-order masking. Rather than proposing new masking gadgets, we focus on hardware-optimized instantiations and integration of state-of-the-art masked components, including masked domain conversions, sampling, and message decoder. In addition, we propose an optimized masked decomposition algorithm with a formal security proof, reducing the number of required operations compared to prior approaches. The complete implementation was functionally verified against the reference software implementations and evaluated on an Field Programmable Gate Array (FPGA) platform. Side-channel resistance was assessed using the Test Vector Leakage Assessment (TVLA) methodology, showing no first-order leakage under the tested conditions. To facilitate reproducibility and further research, we publicly release the full hardware source code together with the collected side-channel trace datasets.

Fault injection (FI) attacks on embedded neural network (NN) implementations primarily focus on inducing misclassification by corrupting weights or intermediate computations, overlooking their interaction with algorithmic adversarial threats. In this work, we present a cross-level attack that bridges implementation-level physical faults to algorithm-level adversarial attacks. By characterizing fault-induced data perturbations during NN inference, we connect FI with backdoor learning, enabling system-level attacks that jointly exploit implementation- and algorithm-level vulnerabilities. Specifically, we propose a precise fault-injection method that reliably manipulates targeted register values to tractable states during execution. Leveraging this level of FI precision, we propose a novel end-to-end feature map-level backdoor attack, where physically induced intermediate perturbations serve as stealthy triggers. Unlike conventional input-based backdoors, our trigger is activated only under physical faults, causing the NN to exhibit adversarial behavior that compromises system integrity while remaining benign during normal operation. We demonstrate that such physically triggered backdoors can be mounted on embedded NN platforms and remain effective against existing backdoor defenses that typically assume input-space triggers. We showcase the attack practicality using electromagnetic FI on convolutional neural networks implemented on ARM Cortex-M4 microcontroller, which is a common platform for constrained embedded applications. Our results highlight a novel attack vector at the intersection of hardware and algorithmic levels, stressing the need for defenses across abstraction levels.

At Crypto 2023, El hirch et al. introduced the cryptographic permutation GASTON. They showed that by using the same number of bitwise operations of ASCON-p - the permutation underlying the new NIST standard ASCON for lightweight authenticated encryption - it is possible to build a permutation that has better resistance against differential and linear cryptanalysis. This makes GASTON an interesting alternative in cryptographic applications. In this paper, we compare GASTON and ASCON-p in terms of resource usage on FPGA and ASIC. Our results show that, despite their similar theoretical costs in bitwise operations, GASTON requires more resources on certain platforms. Additionally, we evaluate the side-channel resistance of the Ascon mode when instantiated with GASTON instead of AScON-p. To this end, we perform correlation power analysis and template attacks using a hardware implementation running on an FPGA platform. By comparing our attack results with an earlier study on AscoN performing correlation power analysis, we observe that the mode instantiated with GASTON achieves a lower success rate for both attacks. This suggests that using GASTON as the underlying permutation improves resistance to this class of attacks.

Neural networks have become a fundamental component of numerous practical applications, and their implementations, which are often accelerated by hardware, are integrated into all types of real-world physical devices. User interactions with neural networks on hardware accelerators are commonly considered privacy-sensitive. Substantial efforts have been made to uncover vulnerabilities and enhance privacy protection at the level of machine learning algorithms, including membership inference attacks, differential privacy, and federated learning. However, neural networks are ultimately implemented and deployed on physical devices, and current research pays comparatively less attention to privacy protection at the implementation level. In this paper, we introduce a generic physical side-channel attack, ScaAR, that extracts user interactions with neural networks by leveraging electromagnetic (EM) emissions of physical devices. Our proposed attack is implementation-agnostic, meaning it does not require the adversary to possess detailed knowledge of the hardware or software implementations, thanks to the capabilities of deep learning-based side-channel analysis (DLSCA). Experimental results demonstrate that, through the EM side channel, ScaAR can effectively extract the class label of user interactions with neural classifiers, including inputs and outputs, on the AMD-Xilinx MPSoC ZCU104 FPGA and Raspberry Pi 3 B. In addition, for the first time, we provide side-channel analysis on edge Large Language Model (LLM) implementations on the Raspberry Pi 5, showing that EM side channel leaks interaction data, and different LLM tokens can be distinguishable from the EM traces.

Masking is a commonly used countermeasure against side-channel attacks, encoding secrets into multiple shares such that each share leaks only partial information. A longstanding question is under what noise conditions masking guarantees security, and how this security scales with the number of shares. While sufficient conditions have been known for binary fields and in high-noise regimes, the borderline and low-noise cases have remained poorly understood. In this work, we close this gap through a decomposition-based analysis. Our approach reduces leakage in extended fields to binary projections, enabling tight bounds on the adversary’s success rate and yielding an optimal reduction from the noisy leakage model to the random probing model—even in regimes where classical reductions fail. As a central theoretical result, we prove a conjecture of Dziembowski et al. (TCC 2016), showing that for any additive group 𝔾 with largest proper subgroup ℍ , masking strictly improves security whenever the leakage is δ -noisy with δ < 1 - |ℍ||𝔾| . We additionally demonstrate the practical relevance of our framework for leakage certification and for determining the required masking order under realistic low-noise conditions. Our results unify and sharpen the understanding of noise requirements for masking, advancing both the theoretical foundations and the practical evaluation of side-channel countermeasures.

Voltage fault-injection attacks are a practical and widely studied fault-attack vector that introduces brief, precisely timed disturbances into an embedded system's power supply to induce errors or bypass security mechanisms in its digital logic. Conventional measures to prevent power disruption typically involve power-filtering circuits and voltage supervisors that detect deviations from normal voltage ranges and respond by resetting the system, but advanced glitch attacks can be short and subtle enough to evade them while still causing exploitable faults. This work proposes a deep learning-based approach that leverages clock signal behavior as a more reliable indicator of system integrity under glitch attacks. Rather than monitoring voltage directly, the model learns to identify malicious glitches through their measurable impact on clock waveforms and recovery patterns. Even when voltage anomalies are too brief to detect, glitches leave longer observable traces in the clock signal. Training on a labeled range of different glitch clock signals enables models to learn subtle patterns, offering more accurate and adaptive anomaly detection than fixed thresholds. Moreover, voltage-regulating components are often removed to increase susceptibility to glitches and bypass threshold-based detection, which in turn amplifies glitch effects on the clock signal and strengthens the model's ability to detect anomalies. The dataset used contains 56 700 glitches of varying intensities in an AES encryption routine running on an STM32F410 microcontroller. Results show that a supervised learning-based clock monitoring approach can effectively identify harmful voltage glitches, providing a foundation for future countermeasures and detection mechanisms.

Over the last decade, applications of neural networks have spread to every aspect of our lives. A large number of companies base their businesses on building products that use neural networks for tasks such as face recognition, machine translation, and self-driving cars. Much of the intellectual property underpinning these products is encoded in the exact parameters of the neural networks. Consequently, protecting these is of utmost priority to businesses. At the same time, many of these products need to operate under a strong threat model, in which the adversary has unfettered physical control of the product. In this work, we present BarraCUDA, a novel attack on general-purpose Graphics Processing Units (GPUs) that can extract parameters of neural networks running on the popular Nvidia Jetson devices. BarraCUDA relies on the observation that the convolution operation, used during inference, must be computed as a sequence of partial sums, each leaking one or a few parameters. Using correlation electromagnetic analysis with these partial sums, BarraCUDA can recover parameters of real-world convolutional neural networks.

Hardening microprocessors against side-channel attacks is a critical aspect of ensuring their security. A key step in this process is identifying and mitigating "leaky" hardware modules, which leak information during the execution of cryptographic algorithms. In this paper, we explore how different leakage detection methods, the Side-channel Vulnerability Factor (SVF) and the Test Vector Leakage Assessment (TVLA), contribute to hardening of microprocessors. We conduct experiments on two RISC-V cores, SHAKTI and Ibex, using two cryptographic algorithms, SHA-3 and AES. Our findings suggest that SVF and TVLA can provide valuable insights into identifying leaky modules. However, the effectiveness of these methods can vary depending on the specific core and cryptographic algorithm in use. We conclude that the choice of leakage detection method should be based not only on computational cost but also on the specific requirements of the system, the implementation of the algorithm examined and the nature of the potential threats.