Silicon carbide (SiC) junction field-effect transistors (JFETs) are promising for high-temperature integrated circuits. However, conventional top-gate structures fabricated in semi-insulating SiC substrates suffer from low threshold voltage (Vth) controllability due to ion-channeling effects and leakage current at high temperature through semi-insulating substrates. In this study, the authors demonstrate an ion-implantation-based SiC JFET architecture that addresses both challenges. By adopting a bottom-gate structure, the deviation between the designed and actual Vth was significantly suppressed to less than 0.1 V at 673 K, owing to the effective compensation of the channeling tail. Furthermore, by integrating the bottom-gate design into a double-well structure on an n-type epitaxial layer, the off-state leakage current at high temperature was thoroughly suppressed by the p-n junction isolation. The leakage current density at 873 K (600 °C) of the double-well p-JFET (∼3×10−5 mA/mm) was much lower than that at 673 K (400 °C) of the p-JFET on the semi-insulating substrate (∼1×10−3 mA/mm).
The deployment of active electronics in extreme environments—such as hypersonic combustion zones and deep supercritical geothermal wells—requires semiconductor devices capable of reliable operation at temperatures exceeding 500 °C. While III-Nitride (III-N) high electron mobility transistors (HEMTs) are theoretically suited for this regime, experimental validation in oxidizing atmospheres remains scarce, with most studies limited to vacuum or inert-gas environments. In this work, we report a new method for the electrical characterization of HEMTs up to 800 °C in an open-air environment. To overcome the challenges of thermal drift and measurement latency at these extremes, we introduce a rapid dual-frequency simultaneous extraction technique, which captures both transfer and output characteristics in a single sweep by modulating the gate and drain voltages at distinct frequencies. Our results demonstrate that the HEMT retains functional gate control, distinct saturation regions, and an on/off ratio exceeding 103 up to 700 °C, significantly outperforming commercial silicon depletion-mode FETs, which exhibited intrinsic carrier failure above 190 °C. Although permanent degradation was observed at 800 °C due to contact metallization failure, the demonstrated survivability up to 750 °C in air provides a critical existence proof for uncooled, non-hermetic electronics, directly supporting the objectives of the DARPA high operational temperature sensors program.
Achieving high on-currents (ID,MAX) and low on-resistances (RON) is a cardinal challenge for ultra-wide bandgap (UWBG) semiconductor materials, such as Al-rich AlxGa1−xN. In this work, we demonstrate state-of-the-art ID,MAX and RON (450 mA/mm and 30.5 Ω mm for LSD = 10 μm) in UWBG Al0.85Ga0.15N/Al0.65Ga0.35N channel high electron mobility transistors. We demonstrate the first microscopic imaging of ohmic contacts to reverse-graded AlxGa1−xN heterostructures and demonstrate high-performance power transistors with a Baliga figure of merit of 629 MW/cm2. We further characterize the high temperature breakdown of these device structures up to 150 °C, showing that high breakdown voltages are maintained with low degradation in RON. Cumulatively, these results show the potential of AlxGa1−xN-channel HEMTs for high voltage and high temperature applications.
Neuromorphic computing based on computing-in-memory architectures requires device platforms capable of high-density integration, low power consumption, and precise analog weight modulation. Memtransistors, which integrate memristive and transistor functionalities within a single device, offer a hardware-efficient route toward compact artificial synapses. Among candidate channel materials, SiGeSn alloys provide unique advantages due to Sn-induced bandgap and strain engineering, mobility enhancement, and electrically tunable defect and short-range order (SRO) effects that enable nonvolatile analog conductance modulation. However, epitaxial growth of SiGeSn is challenged by low Sn solubility and lattice mismatch, necessitating Ge virtual substrates that introduce strain, which complicates intrinsic material characterizations, and leakage, which degrades device performance. Here, we developed a dual-layer epitaxial lift-off process to achieve large-area transfer of 44-nm Si0.08Ge0.85Sn0.07 nanoribbons, enabling strain-relaxed SiGeSn-on-insulator structures with smooth interfaces (RMS ∼0.76 nm) and void-free van der Waals bonding. The process exploits the high etching selectivity between Si and Ge in tetramethylammonium hydroxide, with the Ge buffer serving as an etch stop and subsequently removed through Raman-monitored etching. This approach yields clean SiGeSn-on-insulator structures without thermal or chemical degradation and effectively eliminates substrate-induced strain. Back-gated nanoribbon transistors exhibit ON/OFF ratios up to 1.82 × 103 and a peak hole mobility of 13.5 cm2/V s. With this platform, the investigation of SRO effects on electronic properties is enabled. Additionally, the capability of transferring the ribbons on arbitrary substrates enables its accurate material characterization and provides a scalable pathway for high-performance SiGeSn-based neuromorphic device applications.
In this study, we demonstrate a PEALD-AlN/HfO2 dual-gate dielectric normally-off GaN high-electron-mobility transistor (HEMT) with a recess-tri-gate architecture. By employing a dual-gate dielectric, devices exhibit a superior interface on the 3D gate structure, yielding a field-effect mobility of ∼1083 cm2/V s. Due to improved channel control from the tri-gate architecture, the device achieves a threshold voltage (VTH) of 1.1 ± 0.1 V, a maximum drain current of 854 ± 10 mA/mm, a specific on-resistance of 0.81 mΩ/cm2, a current on/off ratio of more than eight orders of magnitude, and a subthreshold slope of 103 ± 3 mV/decade. In addition to the excellent DC performance, the Negative Bias Temperature Instability (NBTI) of VTH and interface-trap density of the tri-gate MIS-HEMT were systematically investigated to understand the device’s trapping/detrapping behavior. These results culminate in the strong potential of tri-gate GaN metal–insulator–semiconductor (MIS) HEMTs for high-performance enhancement-mode (E-mode) power device applications, while also providing deeper insight into interface behavior in the tri-gate architecture and the associated trapping dynamics under negative-bias-stress conditions.
MnSb is a metallic ferromagnet with a high Curie temperature (∼587 K) and strong spin–orbit coupling, making it attractive for room-temperature spintronic and magnetic sensing applications. We report heteroepitaxial growth of MnSb on GaAs (111) by molecular beam epitaxy, yielding locally epitaxial, strain-relaxed island structures with multiple dominant crystallographic orientations. Structural analysis reveals the coexistence of basal-plane- and pyramidal-plane-oriented domains, enabling investigation of magneto-crystalline anisotropy in an orientationally inhomogeneous ferromagnetic system. Room-temperature magnetic characterization using magnetic force microscopy, scanning nitrogen-vacancy center magnetometry, and angle-dependent ferromagnetic resonance demonstrates a strongly anisotropic, orientation-dependent magnetic response across multiple length scales. Correlating these magnetic responses with crystal structure and local stray fields reveals the role of structural inhomogeneity in governing magnetic anisotropy and spin dynamics in MnSb thin film. These results establish MnSb thin films as a promising platform for vector magnetic-field sensing and orientation-encoded spintronic device concepts.
The effect on the barrier height of inserting ultrathin oxide (GaOx) interlayers at n-type GaN Schottky contacts was systematically investigated. Inserting interlayers (>0.5nm) between GaN and electrode metals having relatively low electronegativities (Al, Ni, and Pd) decreased the Schottky barrier height by 0.2–0.4 eV. On the other hand, a chemically stable Au electrode exhibited almost no changes in barrier height regardless of the presence of an interlayer. X-ray photoelectron spectroscopy analyses revealed that a dipole formed through a redox reaction at the low-electronegativity metal/GaOx interfaces, causing an abrupt energy-band shift and significant change in the Schottky barrier height.
This study presents the thickness-dependent excitonic physics of WSe2 achieved through a precisely controlled reactive ion etching (RIE) process, enabling deterministic thinning from 40 layers down to ten layers on SiO2/Si substrate. This deterministic thickness engineering facilitates a systematic exploration of layer-dependent electronic and optical properties. Detailed Comprehensive characterization confirms the structural integrity, surface uniformity, and stable work-function profile of the etched films. Cathodoluminescence (CL) spectroscopy reveals pronounced band-edge emission features, including neutral and charged excitons, in the ultra-thin regions of the film. Possible transitions from the calculated band structures for varying thin layered WSe2 are estimated by performing density functional theory with correlation of emissions via CL spectroscopy. To evaluate device characteristics, a metal–oxide–semiconductor structure fabricated on the RIE-thinned WSe2 exhibits strong thickness-dependent photo-capacitance, where thicker sections show enhanced photo-response and improved electron inversion even at high frequencies. Low-temperature C–V measurements further highlight robust photoinduced inversion behavior with wide range of probe frequency ∼ 10 kHz to 10 MHz. Overall, this work establishes RIE as a reliable approach for achieving thickness-tailored, high-quality WSe2 suitable for device integration. The combined excitonic physics and tunable photo-capacitance underline its potential for next-generation optoelectronic platforms, including quantum emitters, spin-selective excitonic devices, and quantum photonic architectures.
We investigated effects of nitrogen radical irradiation on device characteristics of vertical β-Ga2O3(010) fin field-effect transistors (FinFETs). A positive shift in threshold voltage with improved in-plane distribution uniformity occurred for nitridated FinFETs due to fixed negative charges formed in nitridated layers on fin sidewalls, indicating that the nitridation treatment can effectively re-establish the post-etched sidewall surface conditions. The breakdown voltage (Vbr) was also uniformly distributed for the nitridated FinFETs, while the specific on-resistance (Ron) was reduced by adopting multi-fin structure and increasing fin width. The nitridated Ga2O3(010) multi-FinFET with a fin width of 300 nm achieved normally off operation with superior device characteristics of a subthreshold swing of 73 mV/decade, an Ion/Ioff ratio of >1010, an Ron of 9.5 mΩ cm2, a Vbr of 1213 V, and a power figure of merit of 1.55 × 108 W/cm2.
We report on the design and experimental demonstration of ultra-wide-bandgap AlGaN polarization-graded field-effect transistors (PolFETs) with ultra-thin channels aimed at enabling high current capability, RF performance, and reduced thermal resistance. Polarization-graded AlGaN layers and ultra-thin pseudomorphic AlGaN buffer layers are employed to achieve low thermal resistance while maintaining high structural quality. The demonstrated PolFETs achieve a maximum soft-saturation drain current density of 800 mA/mm at VG = 4 V and ∼500 mA/mm at VG = 0 V, along with current- and power-gain cutoff frequencies (fT/fmax) of 26/28 GHz, respectively. Small-signal modeling was performed to analyze parasitic and transit delays, and gate-resistance thermometry was implemented to characterize device thermal behavior and benchmark against state-of-the-art AlGaN HEMTs. The ultra-thin AlGaN PolFET exhibits a thermal resistance of 12 K mm/W, representing a significant reduction compared to conventional AlGaN transistor structures. These results demonstrate the feasibility of polarization-engineered ultra-wide-bandgap AlGaN transistors for RF and mm-wave applications, with the added advantage of improved thermal performance.
Neuromorphic computing systems allow electronics to mimic the behavior of biological neurons and hold potential for high-efficiency computation needed for artificial intelligence. One class of electronic units capable of mimicking neural behavior is resistive memory devices, also known as memristors. While the most commonly studied memristors are solid-state in nature, there is a growing interest in the development of ion-rich fluidic memristors since they have a higher level of versatility to mimic biological neurons and synapses, which are themselves fluidic systems with mobile ions as neuroreceptors. Here, we present our work on elucidating the ion transport mechanism in leaf-based capacitive-coupled memristive devices and their use in mimicking habituation, a neural behavior where an organism’s response to repeated applied stimulus diminishes. This work demonstrates the potential that leaf structures hold in serving as biomimetic architecture for the development of highly effective fluidic memristors for simulating neural behavior.
Titanium nitride (TiN) combines metallic optical behavior, thermal stability, and CMOS compatibility, positioning it as a compelling material for next-generation optoelectronics. We demonstrate visible-range broadband photodetectors based on nanostructured black TiN manufactured by using an optimized deposition combined with a simple wet-etching process that allows strong light trapping and low reflectivity (4–15% over 200–900 nm). Under fast 5 V modulation, the black TiN devices exhibit a photocurrent swing nearly twice that of flat TiN, increasing from 55 to 115 μA. This enhancement may be associated with plasmon-induced hot-carrier effects. Under slow 0.5 V illumination, the increase is more modest (22–33 μA), indicating that the plasmonic enhancement strongly depends on the excitation dynamics. Quantitative analysis yields ON/OFF ratios close to unity (∼1), responsivities in the range of 10−4–10−3 A/W, and detectivities up to ∼3×105 Jones. These results indicate that performance enhancement in black TiN is influenced by excitation conditions and carrier dynamics rather than solely by static absorption, establishing black TiN as a scalable platform for visible-range broadband photodetection and optical sensing.
Gallium nitride (GaN) technology has expanded beyond its established roles in high-power and high-frequency switching to become a credible platform for monolithic logic and smart power integrated circuits. This transition is driven by the need to co-integrate level shifting, gate driving, sensing, and protection circuits in close proximity to high-voltage GaN switches, thereby reducing parasitic interconnections and improving robustness under high-dV/dt transients and harsh-environment operation. This work reviews the evolution of GaN-based logic from early D-/E-mode AlGaN/GaN HEMT demonstrations to more manufacturable integration solutions enabled by E-mode technologies, including p-GaN gate HEMTs, recessed MIS-HEMTs, and emerging p-channel device concepts. Major GaN logic families, including direct-coupled FET logic (DCFL), resistor–transistor logic, pseudo-complementary FET logic, bootstrap logic, and complementary logic (CL), are evaluated in terms of voltage swing, noise margin, static power consumption, area efficiency, and suitability for co-integration with power HEMTs. The two most prevalent families, DCFL and CL, are further benchmarked using normalized output swing, noise-margin balance, and transistor current capability to clarify key design trade-offs across reported platforms. Finally, remaining barriers to large-scale GaN digital integration are discussed, including limited p-channel device performance, leakage control at low supply voltages, reliable on-chip rectification for bootstrapped nodes, and reliability-centric circuit/device co-design for high-field and high-temperature operation.
In this work, we demonstrate lateral GaN Schottky superjunction diodes using a p–n–p layer structure. The lateral nature of these devices circumvents the difficulties in achieving charge balance with etch and regrowth techniques. The p–n–p layer Schottky superjunction diodes are compared to reference lateral Schottky diodes on n-GaN to demonstrate the effect of net dopant balance in reverse bias, which resulted in an ∼80× improvement in breakdown voltage with the charge balanced layers with no degradation in the forward on-state characteristics.
High-quality Sn-doped (010) β-Ga2O3 homoepitaxial drift layers were grown by using the low-pressure chemical vapor deposition (LPCVD) method using solid elemental Sn as the n-type dopant source and integrated into vertical Ni/β-Ga2O3 Schottky barrier diodes to evaluate their device-level performance. β-Ga2O3 films with net carrier concentrations spanning from 2.0 × 1016 to 3.2 × 1017 cm−3 were achieved in thick epilayers exhibiting smooth surface morphology and high crystalline quality, as evidenced by surface rms roughness as low as 2.17 nm and an x-ray diffraction rocking-curve full width at half maximum as low as 38.9 arcsec. The fabricated diodes exhibited clear rectification and near-ideal thermionic-emission behavior, yielding ideality factors of 1.16–1.18 and Schottky barrier heights of 1.08–1.19 eV. The differential specific on-resistance (Ron,sp) decreased with increasing carrier concentration, with measured values ranging from 38.07 to 27.31 mΩ cm2. Temperature-dependent current–voltage measurements ranging from 25 to 250 °C showed stable thermionic-emission-dominated transport, with a gradual reduction in Schottky barrier height and an increase in on-resistance due to phonon-limited mobility. Capacitance–voltage (C–V) analysis confirmed uniform and controllable doping profiles and yielded barrier heights between 1.12 and 1.29 eV, depending on carrier concentration. Temperature-dependent C–V measurements revealed a systematic reduction in built-in potential and barrier height with increasing temperature. Reverse-bias measurements demonstrated a breakdown voltage of 225 V for a diode with a drift-layer carrier concentration of 2.0 × 1016 cm−3 in the absence of any field-management structures, with two-dimensional Silvaco technology computer-aided design (TCAD) electrostatic simulations revealing peak electric fields localized at the Schottky anode edge, indicating edge-field-limited breakdown. These results demonstrate LPCVD as a viable approach for the growth of Sn-doped β-Ga2O3 drift layers that support high-quality Schottky interfaces with stable operation over a wide temperature range, providing a foundation for continued development of β-Ga2O3 high power devices.
Valleytronic devices show great promise for next-generation information technology, yet their practical development is limited by the lack of intrinsic ferrovalley materials. To address this issue, we propose an efficient bottom-up strategy to design high-performance two-dimensional (2D) ferrovalley materials, constructing a series of hexagonal metal–organic frameworks (MOFs) from trigonal bipyramidal TMCu4 magnetic clusters (TM = Ta, W, Os, Ir, Re) and organic linker C4H4P2. First principles calculations confirm that these 2D MOFs feature large magnetic anisotropy and robust spontaneous valley polarization. In particular, both freestanding and h-BN-supported Ir–W-based MOFs exhibit large Berry curvatures with opposite signs and distinct magnitudes at the K and K′ valleys. Furthermore, we demonstrate that the intrinsic valley polarization can be reversibly switched by external electric and magnetic fields, enabling potential applications in valleytronic devices.
In this article, we study the effect of the doping level in the intermediate layer of a pseudo-vertical GaN-based p-i-n diode. By decreasing the doping level, from 1.1 × 1016 to 1.6 × 1014 cm−3, we show that the OFF-state capacitance can be reduced by a factor 2.2, without affecting the ON-state resistance too much, which is increased by only 16%. The main consequence is an increase in the cutoff frequency by a factor 1.8, from 137 ± 5 to 250 ± 16 GHz. The DC characteristics of the diode are preserved since no significant variation of the turn on voltage has been found and no breakdown occurs for up to −200 V biasing.
GaN-based power devices have great potential for medium-to-high voltage applications. In this work, we present the device design of a vertical GaN-on-GaN PN power diode using a double field plate structure and guard-rings for electrical field management to achieve a 10 kV breakdown voltage. Simulations show that this device design with a 75 μm thick drift layer and a doping density of 1 × 1015 cm−3 has a breakdown voltage of 10.5 kV and ∼90.5% electrical field management efficiency. Experimentally, the fabricated diode with a ∼74 μm thick drift layer and Nd–Na concentration of 1 × 1015 cm−3 demonstrates a breakdown voltage of 10.3 kV on a bulk GaN substrate. The device has an on-resistance of 8 mΩ cm2 and a Baliga figure of merit of 13.3 GW/cm2. Compared to the theoretical breakdown voltage of this device design, the fabricated device has an overall breakdown efficiency of 89%.
We have fabricated lateral β-Ga2O3 MOSFETs on a 2″ (010) substrate with peripheries ranging from 100 μm to 2 mm and an overall yield of 84.5% (over 95% excluding edge dies). Devices featured source–drain spacings of 1, 2, and 5 μm with regrown ohmic contacts and scaled T-gates. 1 μm devices had Ron as low as 24 Ω · mm and 5 μm devices showed Vbk as high as 863 V. Average fT and fmax for 1, 2 and 5 μm devices were 7 ± 2, 6 ± 1, and 3.7 ± 0.7 and 22 ± 4, 17 ± 3, and 9 ± 0.9 GHz, respectively. Under large-signal operation, a 2 mm-periphery, 2 μm device demonstrated a Pout value of 467 mW (26.7 dB) at 5 GHz, the highest reported net RF power for a Ga2O3 transistor. Aggregate device performance was analyzed and sources of device failure and performance degradation were identified, including short-channel effects and gate leakage. These results demonstrate the viability of β-Ga2O3 MOSFET fabrication on large-area substrates and provide insight into technical barriers in manufacturability.
