In this study, we present a GaN-on-Si pseudo-vertical p-n diode fabricated using selective area growth (SAG). The device achieved a high current density of 1.5 kA cm(-2) and a low specific on-resistance (R-on,R-sp) of 3.3 m Omega cm(2). A very high on/off current ratio (I-on/I-off) of 1012 was also recorded. Notably, for the first-time using SAG, uniform avalanche breakdown behavior of 850 V was demonstrated through temperature-dependent reverse bias measurements, corresponding to a Baliga figure of merit of 0.2 GW cm(-2). These results emphasize the advantages of localized epitaxy in achieving high-quality p-n junctions on Si substrates, paving the way for scalable, high-performance GaN power devices monolithically integrated with Si technology. To evaluate the influence of geometric parameters on epitaxial quality and device performance, the mesa spacing was systematically varied while keeping the diameter fixed. Optimal results were obtained with 5-15 mu m spacing, offering the best trade-off between forward conduction efficiency and reverse blocking robustness. This comprehensive investigation underscores the importance of geometric optimization and localized epitaxy in advancing high-performance GaN-on-Si p-n diodes for next-generation power applications.

In this article, we study the effect of the doping level in the intermediate layer of a pseudo-vertical GaN-based p-i-n diode. By decreasing the doping level, from 1.1 × 1016 to 1.6 × 1014 cm−3, we show that the OFF-state capacitance can be reduced by a factor 2.2, without affecting the ON-state resistance too much, which is increased by only 16%. The main consequence is an increase in the cutoff frequency by a factor 1.8, from 137 ± 5 to 250 ± 16 GHz. The DC characteristics of the diode are preserved since no significant variation of the turn on voltage has been found and no breakdown occurs for up to −200 V biasing.

In this study, we demonstrate avalanche breakdown in pseudo-vertical GaN power devices grown by selective area growth (SAG) on 200 mm Si substrates, offering a pathway to high performance with silicon fab compatibility and low cost compared to GaN-on-GaN devices. A 1.5 & times; 1016 cm-3 silicon-doped GaN drift layer enabled the fabrication of an 805 V pseudo-vertical p-n diode. Device stability was initially evaluated by performing temperature-dependent reverse bias measurements (298-373 K) alongside DC stress conducted near the avalanche threshold. In the absence of dedicated edge termination, the peak electric field concentrates at the p-n junction sidewalls, triggering impact ionization and avalanche breakdown. Extended stress induces hard breakdown-driven by thermo-mechanical degradation-confirmed by post-failure SEM analysis. TCAD simulations corroborate the role of sidewall field enhancement in both avalanche initiation and failure mechanisms.

Edge termination techniques play a crucial role in enhancing the breakdown voltage (BV) and managing electric field distribution in GaN-based power devices. This review explores six key termination methods—field plate (FP), mesa, bevel, trench, ion implantation, and guard ring (GR)—with a focus on their performance, fabrication complexity, and insights derived from TCAD simulations. FP and trench terminations excel in high-voltage applications due to their superior electric field control but are accompanied by significant fabrication challenges. Mesa and bevel terminations, while simpler and cost-effective, are more suited for medium-voltage applications. Ion implantation and GR techniques strike a balance, offering customizable parameters for improved BV performance. TCAD simulations provide a robust framework for analyzing these techniques, highlighting optimal configurations and performance trade-offs. The choice of edge termination depends on the specific application, balancing BV requirements with manufacturing feasibility. This review offers a comprehensive comparison, emphasizing the critical role of simulations in guiding the selection and design of edge termination techniques for GaN power devices.

In this study, the impact of surface treatment by TMAH and HF on the electrical characteristics of GaN-on-GaN Schottky diodes is examined through I–V and C–V characterizations. A TMAH surface treatment leads to an improvement in the reverse characteristics of the devices and improvement in breakdown voltage (BV) by almost 200 V compared to HF treatment. Additional XPS characterizations reveal a reduction in both O and C concentration from the surface due to TMAH treatment. When combined with proper edge termination techniques, this approach can help achieve breakdown voltages that are closer to the theoretical limits.

This article compares the impact of different freestanding GaN substrates on the material and electrical properties of Schottky diodes. Material characterization using cathodoluminescence and Raman spectroscopy was performed to analyze defects in the wafers. Randomly distributed clusters of dislocations were observed in one sample, whereas the other sample was free of such clusters. Schottky diodes were subsequently fabricated on these wafers and electrically characterized to investigate the influence of material characteristics on key device parameters, including barrier height, ideality factor, on-resistance, leakage current, and breakdown voltage. A lower barrier height, higher ideality factor, and lower breakdown voltage were observed in the sample with clusters.

In this article, we propose a high-frequency model taking into account the series resistance of pseudo-vertical gallium nitride (GaN)-based p-i-n diodes. This model relies on the specific contact resistance on p-type GaN and the sheet resistance of the bottom n-type GaN. Those two quantities are obtained while fitting the RF experimental data and are slightly different from the dc values. The interest of this model is that the effective values, at the working frequency instead of “only” the dc values, are extracted using only a few devices. The novelty of the work resides in the consideration of the geometrical dimensions of the diode (anode radius and distance between anode and cathode) in the model. Furthermore, the model allows the determination of the most limiting geometrical parameters and can predict the series resistance of other topologies. In the present case, we show the most limiting factor is the radius of the anode due to the difficulties of achieving low specific contact resistance on p-type GaN. The parasitic capacitance is also extracted using the measured devices, allowing the modeling of the effective capacitance as a function of the frequency.

In this study, we introduce a 5 mu m-thick GaN-on-Si pseudo-vertical p-n diode grown with Selective Area Growth (SAG), which exhibits a soft breakdown voltage of -240 V. For the first time, we measured temperature-dependent current-voltage characteristics in the range of 303 to 413 K to explore the origin of leakage conduction in a p-n diodes fabricated via SAG. At low reverse bias levels (0 to -20 V), the primary conduction mechanism is identified as Frenkel-Poole Emission (FPE). In contrast, at higher voltages, up to -100 V, the dominant mechanism shifts to Variable Range Hopping (VRH) throughout the entire temperature range. Additionally, we conducted TCAD simulations and employed Lock-in Thermography (LiT) to investigate the origin of the leakage current and localize it.

GaN is an interesting material for power application but requires increasing process reliability. In this work, Au/ Ni ohmic contacts on p-type GaN are studied over a complete process flow representative of a real die fabrication. The impact of passivation and refill layers on the contact quality are investigated. First results reveal that Si based passivation degrades the ohmic behavior whereas Parylene passivation allows to keep the contact integrity. The addition of Al refill layer has only a slight impact on the best I-V characteristics. After a complete stack process, composed of two passivation and two refill layers, only fully Parylene passivated samples lead to an ohmic contact with a quasi-linear I-V response and a corresponding average SCR value of 0.96-2.79 x 10-3 Omega cm2.

Aluminum scandium nitride barrier layers increase the available sheet charge carrier density in gallium nitride-based high-electron-mobility transistors and boost the output power of high-frequency amplifiers and high voltage switches. Growth of AlScN by metal-organic chemical vapor deposition is challenging due to the low vapor pressure of the conventional Sc precursor Cp3Sc, which induces low growth rates of AlScN and leads to thermally-induced AlScN/GaN-interface degradation. In this work, novel Sc precursors are employed to reduce the thermal budget by increasing the growth rate of the AlScN layer. The AlScN/GaN interfaces are investigated by high-resolution X-ray diffraction, high-resolution transmission electron microscopy, time-of-flight secondary ion mass spectrometry, capacitance-voltage, current-voltage and temperature-dependent Hall measurements. Linearly graded interlayers with strain-induced stacking faults, edge, and screw dislocations form at the AlScN/GaN interface at growth rates of 0.015 nms-1. Growth rates of 0.034 nms-1 and higher allow for abrupt interfaces, but a compositional grading in the barrier remains. Homogeneous barrier layers can be achieved at growth rates of 0.067 nms-1 or by growing an AlN interlayer. The electrical properties of the heterostructures are sensitive to Sc accumulations at the cap/barrier interface, residual impurities from precursor synthesis, and surface roughness. This study paves the way for high-performing devices. Low growth rates in AlScN/GaN heterostructures grown by metal-organic chemical vapor cause the formation of linearly graded interlayers and degradation of the electrical characteristics. Growth rates are enhanced with novel Sc precursors, and high interface abruptness and homogeneous layers are achieved. Structural quality strongly affects the performance of the 2D electron gas, which is the core of high-electron-mobility transistors. image

In this work, a GaN-on-Si quasi-vertical Schottky diode was demonstrated on a locally grown n-GaN drift layer using Selective Area Growth (SAG). The diode achieved a current density of 2.5 kA/cm2, a specific on-resistance RON,sp of 1.9 mΩ cm2 despite the current crowding effect in quasi-vertical structures, and an on/off current ratio (Ion/Ioff) of 1010. Temperature-dependent current–voltage characteristics were measured in the range of 313–433 K to investigate the mechanisms of leakage conduction in the device. At near-zero bias, thermionic emission (TE) was found to dominate. By increasing up to 10 V, electrons gained enough energy to excite into trap states, leading to the dominance of Frenkel–Poole emission (FPE). For a higher voltage range (−10 V to −40 V), the increased electric field facilitated the hopping of electrons along the continuum threading dislocations in the “bulk” GaN layers, and thus, variable range hopping became the main mechanism for the whole temperature range. This work provides an in-depth insight into the leakage conduction transport on pseudo-vertical GaN-on-Si Schottky barrier diodes (SBDs) grown by localized epitaxy.

Laser Thermal Annealing (LTA) is a key process step to improve the 4H-SiC devices by reducing their on-state resistance. In this study, we investigate the electrical, structural and morphological properties of nickel contact fabricated by LTA. A contact formed by a classical Rapid Thermal Annealing (RTA) was also fabricated as reference. Based on structural analysis, the phases formed by LTA do not match with RTA sample ones that has better ohmic properties. Nevertheless, the LTA contacts reach a specific contact resistance of 2.4×10 -5 Ω.cm 2 for an annealing at 4.75 J.cm ‑2 , which represents a significant improvement in comparison with our previous contacts fabricated with the same experimental protocol using titanium.

In this study, pseudo-vertical GaN-on-Sapphire PiN diodes with different mesa radii were designed, fabricated and characterized. First, critical process stages, such as mesa etching, ohmic contacts on GaN and passivation, are presented and reviewed to obtain functional diodes. Ion beam etching, with an optimized USG hard mask, seems the best solution to achieve reliable devices. Our results also show the impact of different passivation solutions on Au/Ni ohmic contact. Finally, the diodes with varying radii of the mesa (20, 40 and 60 mu m) exhibit turn-on voltages of approximately 3.5 V and achieve a specific on-resistance of 0.56-1.7 m ohm center dot cm(2). More, the devices show low capacitance versus frequency properties up to 40GHz. Further adjustments on designs and fabrication processes are requested to enhance performance.

This study focuses on the impact of negative fixed charge, achieved through fluorine (F) implantation, on breakdown voltage (BV) enhancement in vertical GaN Schottky diodes. Several device and implant-related parameters are examined using Synopsys Sentaurus TCAD simulations in order to determine the optimum fixed negative charge concentration required to achieve the highest BV. The simulated structure consisted of a Schottky diode with a box consisting of negative fixed charges to achieve the edge termination of the Schottky device. An empirical equation is proposed to determine the optimum fixed charge concentration for the highest BV based on depth. The simulation also considered implantation profiles derived from SIMS data from an actual device implanted with multi-energy and multi-dose F. It is demonstrated that the BV has a similar dependence on the key parameters like in the box profile. In summary, this work provides valuable insights into optimizing edge termination techniques using negative fixed charge for improved BV in vertical GaN power devices.

AlN nucleation layer is the key issue for the performance of GaN high frequency telecommunication and power switching systems fabricated after heteroepitaxy on Silicon or Silicon Carbide. In this work, we demonstrate and explain both the low level and the origin of propagation losses in GaN/3C-SiC/Si High Electron Mobility Transistors (HEMTs) at microwaves frequencies, in view of providing efficient circuits. First, it is shown that the use of 3C-SiC as an intermediate layer between the Si substrate and the GaN epitaxial layer drastically decreases RF propagation losses. Using Secondary Ion Mass Spectroscopy (SIMS) measurements, we demonstrate that dopant in-diffusion (both Al and Ga) into the 3C-SiC pseudo-substrate remains confined beneath the interface. Furthermore, by combining scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM), the 2D profile shows the presence of a slightly conductive zone beneath the AlN/3C-SiC interface that is highly limited (less than 50 nm) whatever the growth conditions of the (Al, Ga)N layers on 3C-SiC explaining the low propagation losses obtained for such devices. This behavior differs from the one previously observed for GaN growth on Si substrate. This work demonstrates the importance and efficiency of the 3C-SiC intermediate layer when used as a pseudo-substrate increasing not only the crystalline quality of the subsequent (Al, Ga)N layers but also permits to achieve high potential GaN power devices as it is crucial.

Gas sensors are devices that can detect and/or discriminate gases in their surroundings. Some of these devices are based on vibrating structure covered with a coating sensitive to the species to detect. But such a layer can cause device failures issues like ageing, low reliability and high response time. Nonetheless, gas sensors are of importance for industrial environments in many applications. In addition, in some cases, the sensors must operate in harsh environments, that can lead to a severe degradation of the devices. In this paper, we propose to review different MEMS devices, without any sensitive layer, for gas detection applications. The objective is to measure a physical property of the gas in order to determine its concentration. With the microsystem devices, limits of detection as low as 0.2 % has been obtained, illustrating the capabilities of the structures elaborated. And in our case, due to the absence of sensitive film that must be adapted according to the species to detect, it leads to generic sensors, compatible with many different gases. Moreover, by combining the measures of 2 physical parameters, the discrimination of the gases, with their respective concentrations, is accessible.

The electrical properties of ohmic contacts are classically investigated by using the transfer length method (TLM). In the literature, the TLM patterns are fabricated onto different substrate configurations, especially directly onto the 4H-SiC wafers. But, due to the high doping level of commercial substrates, the current is not confined close to the contact and, in this case, the specific contact resistance (SCR) value is overestimated. In this article, we propose, by the means of simulations, to investigate the influence of the layer under the contact towards the estimation of the SCR. The simulation results highlight that, for an accurate determination of the SCR values, an isolation layer between the contact and the silicon carbide substrate is mandatory. Thus, we have determined the characteristics (doping level and thickness) of a suitable isolation layer compatible with SCR values ranging from 10−3 to 10−6 Ω·cm2.

In this work, we report on the importance of layer distribution after annealing to form a high quality ohmic contact on p-type GaN, using nickel (Ni) and gold (Au) thin layer association. Both the standard GaN/Ni/Au and its reverse, GaN/Au/Ni on p-type GaN were studied. The Au/Ni stack exhibits the most promising results in this study. While the standard GaN/Ni/Au contact exhibits a quasi-linear current-voltage (I-V) characteristic, its counterpart, GaN/Au/Ni, shows pure ohmic behavior, with a specific contact resistance (rho c) as low as 2.0 x 10-4 omega.cm2 after rapid thermal annealing (RTA) at 500 degrees C for 5 min under air ambient, equivalent to the best literature results. X-ray diffraction (XRD) and transmission electron microscopy (TEM) analyses demonstrate the incomplete inversion of layers during annealing leading to a GaN/Ni/Au/NiO stack that explains why GaN/Ni/ Au contact shows inferior electrical performance. On the other hand, for the GaN/Au/Ni contact annealed in the same conditions, the excellent results can be attributed to both (i) the presence of the gold layer at the interface with GaN, allowing the formation of gallide solid solution (Ga-Au) and (ii) the formation of NiO directly contacted with the p-GaN. Those two mechanisms are known to lead to the formation of good ohmic contact on ptype GaN. These results demonstrate that although GaN/Ni/Au is a standard contact for p-GaN layers, the opposite stack (GaN/Au/Ni) gives the best Ohmic behavior. This is important for achieving the best performance of GaN power diodes or transistors including a p-gate structure.