This paper presents a wireless multimodal physiological monitoring application-specific integrated circuit (ASIC) fabricated in the 180 nm process and assembled in an injectable device to measure photoplethysmography (PPG), electrocardiography (ECG), and subcutaneous body temperature of animals. The device miniaturization is achieved by a shared receiver (Rx) coil and inductive link for both wireless power transfer (WPT) and data communication. An optimized folded L-shape Rx coil enhances the quality (Q) factor, coupling with the transmitter (Tx) coil without increasing the device size. To facilitate WPT, the ASIC alternates between recording and low-power sleep modes, achieving 2.54 mu W ultra-low power consumption on average. The ECG analog frontend (AFE) amplifies the ECG signal with an adjustable gain of 45-80 dB and an input-referred noise (IRN) of 0.99 mu VRMS, while the PPG AFE achieves an IRN of 30.8 pARMS. The temperature AFE provides a 27-47 degrees C sensing range with 0.02 degrees C inaccuracy. The AFE outputs are sequentially quantized by a 10-bit analog- to-digital converter (ADC) with 54.7 dB signal-to-noise-and-distortion ratio (SNDR). For reliable data transmission, the ASIC employs a memory-assisted backscatter scheme, storing data in an 8 Mb memory chip and transmitting it when the inductive link is stable. The ASIC functionality has been validated in vivo on anesthetized rats.
This work presents L-Sort, the first localization-based spike sorting accelerator on a miniaturized chip hardware (FPGA). Spike sorting, crucial for neural activity analysis, involves detecting, extracting, and clustering spikes. L-Sort uses geometric data to localize spikes, reducing the need for extensive waveform retention. The system includes a ZCU104 FPGA board and a computer for real-time visualization. Visitors will feed raw Neuropixel data into the FPGA and observe real-time sorted spike trains.
For decades, sequence-to-sequence alignment is a crucial tool in bioinformatics that identifies the similarity between a query and the reference genome sequence. Because one single reference sequence is insufficient to express the diversity of genes, the concept of the reference genome graph has been proposed, which utilizes a graph structure to represent genetic variations and has a better recording of biological information. As results, different sequence-to-graph alignment algorithms have been developed to address the new demand. Although there are several fast methods available, in the regions enriched with genetic variations, the non-heuristic Smith-Waterman method is still the main approach to guarantee finding the optimal solutions at the cost of lengthy processing time. To alleviate this issue, we design a memory-efficient hardware accelerator for variation-enriched sequence-to-graph alignment on an Intel Arria 10 FPGA. According to our experiment, the proposed 128parallel accelerator operates at 200 MHz, and achieves more than 9X speed-ups when compared to the PaSGAL software for the MHC gene dataset in the human genome GRCh38.
Data security has become a critical issue limiting the rapid development of Wireless Body Area Networks (WBANs). Conventional encryption methods are considered not feasible for WBAN scenarios due to the complexity of the algorithms. Physiological signal-based encryption methods are believed to be potential solutions for WBANs due to the natural randomness of the data. However, physiological data has the drawbacks of high correlation and small key space within a short period. In this paper, a novel Electrocardiogram (ECG)based dynamic encryption scheme for WBANs is proposed. By utilizing the similarity of ECG features in various locations, a novel key distribution method based on security templates is proposed to synchronize the key seeds securely. Then, the designed multidimensional chaotic system dynamically generates key sequences by synchronizing key seeds among different nodes to en/decrypt the information in WBANs. The validation and analysis results demonstrate that the scheme has the advantages of large key space, high randomness and robustness, and low latency compared to the existing methods.
This paper shows a circuit concept for low-energy neuromorphic hardware for Spiking Neural Networks (SNNs). Combining continuous time-encoded values with time-discrete circuitry helps to improve energy-efficiency. Simple design blocks for neurons and synapses make a scalable neural network design process possible. The direct connection between neurons and synapses in an analog manner reduces latency and energy consumption. The functionality was proven by a small neural net solving a classification problem on silicon. Measurements show a FOM of 86.9 fJ for one synaptic operation.
