Partial differential equation (PDE) eigenvalue problems have broad applications in science and engineering. The Locally Optimal Block Preconditioned Conjugate Gradient (LOBPCG) method is widely regarded as one of the most efficient eigensolvers in practice. However, GPU-accelerated LOBPCG for PDE eigenvalue problems–particularly when discretized using high-order/spectral finite element methods (HOSFEM)–faces performance bottlenecks, including slow convergence, inefficient memory access, and workload imbalance. This paper aims to develop an efficient GPU-accelerated LOBPCG solver for generalized PDE eigenvalue problems arising from HOSFEM discretizations, addressing the challenges through a series of optimizations targeting both convergence acceleration and per-iteration efficiency. First, we improve convergence by introducing an optimized orthogonalization procedure with minimal overhead. Second, we enhance per-iteration performance by offloading more computations to the GPU and introducing two custom kernels: (1) LOB_SpMM, a sparse matrix–dense matrix multiplication kernel using two-dimensional tiling, outer-product computation, and sparsity-aware load balancing; and (2) mKn_GEMM, an irregular matrix multiplication kernel that exploits input matrix structure for efficient task partitioning and reduction. Numerical experiments demonstrate significant performance gains: compared to the state-of-the-art implementation in HYPRE, our optimized LOBPCG solver achieves speedups of 3.75 × to 91.43 × on the V100 GPU and 2.10 × to 92.59 × on the A100 GPU.
High-performance computing (HPC) systems are increasingly heterogeneous, requiring developers to balance platform-specific optimizations with code portability. SYCL (a standard, single-source C++ programming model) addresses this by abstracting hardware diversity into single-source code that can run across CPUs, GPUs, and other accelerators. Therefore, porting a classical HPC benchmark to SYCL and assessing the challenges, limitations, and performance are essential to understand the practical implications of adopting SYCL in real-world scientific applications. While previous porting work has largely focused on using automated tools like the Intel DPC++ Compatibility Tool (DPCT), less attention has been paid to the practical challenges of manual porting. In this paper, we evaluate the portability and performance of SYCL by porting the LULESH (Livermore Unstructured Lagrangian Explicit Shock Hydrodynamics) proxy application from CUDA to SYCL. This study explores two migration strategies: the automated approach using DPCT and a manual code refactoring approach. We provide insights into the difficulties encountered during the porting process and the corresponding solutions. Performance results demonstrate that both SYCL implementations of LULESH achieve competitive performance compared to the original CUDA version on single-GPU configurations. We compare oneAPI and AdaptiveCpp using a manually refactored LULESH, and observe notable performance differences. Additionally, when running on CPUs with Message Passing Interface (MPI) across multiple processes, the SYCL versions achieve an average speedup of approximately 3.7 × over the OpenMP baseline. In contrast, initial multi-GPU tests reveal significant MPI overheads, indicating that efficient scaling across GPUs remains a challenge.
With the hardware architectures booming over the last decade, the newly-introduced Tensor Core Unit (TCU) on GPU has empowered the process of AI training and inference more efficiently. Although TCU is prevalent and promises a significant increase in performance, they suffer from over-specialization as only matrix multiplication(MM) on small matrices is supported. Due to the diversity of non-MM operations and the limitation of asymmetric MM configuration, previous works only achieved limited success in bridging performance-critical kernels such as stencil computation with FP64 Tensor Cores. They either restrict the stencil parameters, rely solely on low precision, or require extensive changes to the data layout. This paper presents a practical runtime technique, Cladder, for tensorizing traditional Stencil computation to efficiently use versatile TCU while preserving the original accuracy and data layout. Without restricting the stencil parameters, Cladder formulates an efficient mapping of the Stencil computation with a series of tensor operations to leverage the computing power of TCU. To improve the data reuse through the GPU memory hierarchies, a two-level accessing optimization technique, temporal kernel fusion, is proposed innovatively, leading to less data movement and more register saving in a cohesive fashion. Moreover, Cladder identifies the spatial and temporal dependencies carefully, adapts stencils in different shapes to tensors, and paves a generalized way for achieving practical tensorization on Stencil. Experiments demonstrate that Cladder could provide a practical solution for leveraging TCU in Stencil-driven scientific computing and achieve superior performance compared to the related state-of-the-arts.
Achieving high performance for matrix multiplication (GEMM) remains critical in high-performance computing (HPC) and machine learning (ML). As core computational components, micro-kernels determine GEMM efficiency but face challenges in development cost and hardware adaptability—especially on modern General-Purpose DSPs (GPDSPs) with VLIW and SIMD architectures. Existing automatic micro-kernel generation methods on DSP platforms either suffer from suboptimal performance due to general compiler backend limitations or face challenges in handling complex VLIW instruction scheduling and cross-platform adaptability. This paper proposes MAGGIE, an MLIR-based automatic micro-kernel generation approach for GPDSPs that uses a progressive lowering design at two levels: generic optimization (i.e., algorithmic transformations and intermediate code optimization) and backend specialization (i.e., DSP-specific instruction scheduling and memory access fusion). Experimental results on the FT-M7032 DSP platform demonstrate that automatically generated micro-kernels achieve a peak efficiency of 99.2
Dense linear algebra kernels—General Matrix Multiplication (GEMM), Triangular Solve with Multiple Right-Hand Sides (TRSM), and LU decomposition with partial pivoting (GETRF)—serve as foundational computational building blocks for both High-Performance Computing (HPC) and modern Artificial Intelligence (AI). While highly optimized implementations exist for CPUs and GPUs, emerging Neural Processing Units (NPUs) present unique architectural challenges that demand novel algorithmic approaches to achieve peak performance. The Huawei Ascend 910 NPU exemplifies these challenges: each of its 20 AI cores integrates heterogeneous functional units (Cube, Vector, Scalar) capable of concurrent execution. This architecture enables theoretical performance beyond linear core scaling, but only if algorithms can coordinate fine-grained parallelism across these units while addressing complex memory hierarchies. This paper makes following contributions: (1) New Parallelism Discovery Scheduling We identify and formalize previously unexplored parallelism in TRSM and GETRF kernels, then design a provably efficient scheduling strategy to map these opportunities onto the Ascend 910’s heterogeneous units (Cube/Vector/Scalar). This breaks performance limits imposed by core-count scaling. (2) Unified Data Partitioning Strategy We extend traditional communication optimality analyses to the Ascend 910’s intricate cache hierarchy, which features a mix of shared, distributed, inclusive, and exclusive caches. Our unified partitioning strategy achieves asymptotic communication optimality under these complex constraints. Autonomous On-Device Scheduling We develop an autonomous scheduling mechanism that offloads tiling parameter computation entirely to the device, minimizing host-device communication overhead and enabling efficient on-device kernel fusion. Notably, our work establishes the first high-performance algorithmic baseline for TRSM and GETRF on the Ascend NPU platform, addressing a critical gap in the existing ecosystem. To validate our approach, we implement the kernels integrated with these techniques on the Ascend 910 NPU, achieving consistent speedups of 2-3 × over the highly optimized NVIDIA A100 cuBLAS/cuSolver library and MAGMA. Remarkably, this performance is achieved despite the Ascend 910’s comparable theoretical FLOPS and lower memory bandwidth relative to the A100. These results demonstrate that algorithmic innovation can unlock the full potential of NPUs, enabling them to outperform state-of-the-art GPUs in dense linear algebra tasks, even without superior raw hardware specifications. This work significantly broadens the applicability of NPUs for HPC and AI workloads, challenging the notion that performance is inherently tied to core count or peak hardware capabilities.
