The escalating performance demands of modern applications are driving the High-Performance Computing (HPC) industry toward massive, heterogeneous systems designed to tackle increasingly diverse workloads. As these architectures evolve to incorporate specialized accelerators like GPUs, the underlying software stack has become fragmented and complex, significantly burdening the development of distributed applications. In this work, we present a methodology designed to streamline the deployment of high-performance applications on HPC clusters while fully exploiting their heterogeneous compute capabilities. We advocate adopting standard programming interfaces, specifically the C++ Standard Template Library (STL), extended via specialization to support transparently distributed and accelerated execution. Our approach retains flexibility, allowing developers to integrate accelerator-specific languages and frameworks for fine-grained optimization or ecosystem compatibility. To validate our methodology, we present a case study in the life sciences domain: a high-performance, distributed implementation of the Smith-Waterman algorithm. Running on a heterogeneous GPU-accelerated cluster, our solution achieves a performance improvement of up to 5.88× over the current state of the art.
Graph coloring assigns colors to vertices such that no two adjacent vertices share the same color. As graphs grow in size and complexity, scalable graph coloring becomes increasingly challenging. Although many CUDA-based parallel coloring algorithms have been proposed, they often face a quality–performance trade-off: strict priority orderings can reduce the number of colors but limit parallelism. We present CHROMA, a high-quality, efficient, and robust multi-GPU graph coloring framework that consolidates the smallest-degree-first priority-allocation stages in the Jones–Plassmann (JP) algorithm to reduce synchronization overhead. Building on this foundation, CHROMA introduces three optimizations—efficient loop scanning, smallest-degree calibration, and elastic granularity control—to improve coloring quality, reduce runtime, and provide tunable control over the trade-off. CHROMA further integrates a robust graph partitioning strategy to scale across multiple GPUs. Experiments on diverse real-world graphs show that CHROMA achieves up to a 7× geometric-mean speedup on a single GPU over state-of-the-art methods while maintaining competitive coloring quality. We open-source CHROMA to facilitate future research.
Random Forests (RFs) are simple, interpretable, and parallelizable Machine Learning (ML) models, well-suited for deployment on edge devices such as Field-Programmable Gate Arrays (FPGAs). Existing hardware accelerators often exploit both horizontal and vertical parallelism of RFs to improve performance, at the cost of increasing hardware complexity. We propose Hokidachi, a novel RF accelerator architecture that relies solely on horizontal parallelism, reducing memory fragmentation and enhancing compatibility with a wider range of models, while also enabling between 2× and 4× lower inference latencies.
Although fog computing has demonstrated its potential for managing smart grid infrastructure, placing distributed artificial intelligence services on these platforms raises both general and specific challenges. This paper focuses on dynamically allocating resources to place services as they become available (i.e., online). To this end, we define and evaluate Dynamic-Data-and-Learning-Grouping, a new online service placement algorithm. DynDLG is designed to reduce the time and energy consumption of learning services through topological considerations using a distributed learning service model and a fog computing placement model. A significant number of samples produced by a Batsim simulation environment were used to compare DynDLG to a HEFT-based algorithm. The results demonstrate a clear difference between the two approaches, showing that the topological approach of DynDLG outperforms in terms of time and energy consumed by the placed applications.
With the explosive growth of data generated by modern AI and ML workloads, there is a growing push to move computation closer to where data resides (at or near the storage layer) to reduce data movement costs and improve end-to-end performance. However, commercial computational storage devices (CSDs) often provide limited compute capabilities for demanding applications, and designing custom CSD hardware is prohibitively expensive, especially at low production volumes. As a result, researchers and system designers increasingly rely on emulation to explore architectural tradeoffs, prototype new features, and validate functionality before committing to hardware. This paper introduces EmuCSD, a flexible and low-overhead emulation framework for computational storage devices. EmuCSD supports a broad range of applications, allows users to model diverse compute-unit configurations, and can emulate multiple CSDs operating concurrently—capabilities that are critical for evaluating realistic, large-scale data-processing pipelines. The framework enables rapid design iteration, reduces development cost, and provides a practical environment for testing CSD behavior under different computational, storage, and workload scenarios. The experimental results demonstrate both the performance efficiency and functional versatility of EmuCSD, highlighting its value as a general-purpose platform to advance research and development in computational storage systems.
