Background As integrated circuit technology nodes advance, optical proximity effects distort printed patterns and degrade yield. Existing inverse lithography technology (ILT) struggles with multi-scale feature imbalance, sub-resolution assist feature (SRAF) incompatibility with main patterns, and the trade-off among optimization efficiency, printing accuracy, and mask manufacturability. Aim This work proposes an efficient gradient-driven ILT framework to address the above issues, improving printing accuracy, optimization efficiency, and mask manufacturability for advanced technology nodes. Approach We propose MF-ILT, a framework synergizing multi-scale adaptation and frequency-domain segmentation. It integrates two core modules: (1) a statistical multi-scale soft attention (SMSA) mechanism that adaptively fuses multi-scale features via feature variance metrics, avoiding manual weight tuning, and (2) a frequency-domain split SRAF (FS-SRAF) module that generates SRAF in high-frequency edge regions and suppresses isolated artifacts. The framework also adopts an improved hybrid loss function (Huber loss + process variation band regularization) and end-to-end differentiable design to ensure efficient gradient propagation. Results On the ICCAD13 dataset and large-scale layouts, MF-ILT outperforms state-of-the-art (SOTA) methods: compared with gradient-driven methods, the average L2 error achieves a maximum reduction of 35.3%, and edge placement error (EPE) violations decrease by up to 48.6%; compared with deep-learning-based methods, the L2 error drops by 31.4% to 33.4%, and EPE violations decrease by 73.2% relative to the optimal deep-learning-based SOTA. The average optimization time per test case is only 3.1 s, with a peak memory consumption of 3.9 GB. Conclusions MF-ILT provides an efficient and robust ILT solution for advanced technology nodes, with its core modules (SMSA and FS-SRAF) effectively solving multi-scale imbalance and SRAF incompatibility issues while balancing optimization efficiency and mask manufacturability. It lays a foundation for subsequent extensions to large-chip optimization.
Deep reactive ion etching (Bosch process) is a core technology in silicon microfabrication; however, its performance is still limited by outline defects, such as bottom corner height differences. We systematically investigated the influence mechanism of the aforementioned parameters on the bottom-of-trench etching flatness by solely regulating key process parameters during the passivation layer deposition (C4F8) and etching (SF6) stages. These parameters included gas flow rates, time ratios, and bottom radio frequency power. Throughout the process, no other gases, such as chlorine-based gases, were introduced. Only these two gases were employed for process adjustment. Experimental results indicate that optimal bottom flatness is achieved with a C4F8 flow rate of 150 to 350 sccm, an SF6 flow rate of 500 sccm, a passivation/etching time ratio of 1.12:1, and a bottom radio frequency (RF) power of 100 W. In addition, findings reveal that increasing the C4F8 time significantly enhances bottom height differences; increasing the SF6 flow rate initially decreases height differences before causing them to rise again; and bottom RF power below 80 W induces micro-mask effects, whereas power levels above 120 W exacerbate height differences, with 100 W identified as the equilibrium point. We quantify the critical process window, providing a theoretical foundation and process pathways for achieving high-precision control over silicon etching morphology.
Significance High-precision digital maskless lithography is essential for advanced integrated circuit fabrication, but existing mask-design methods struggle to simultaneously achieve superior pattern fidelity and computational efficiency, especially for complex nested structures. Aim We introduce a multistrategy collaborative optimization framework that integrates genetic algorithm, biogeography-based optimization, and tent map-based chaotic mutation to enhance both accuracy and speed in digital photomask design. Approach Building on the Hopkins imaging model and a tailored multiobjective fitness function, the proposed method merges GA's local search with BBO's global migration strategy. To accelerate convergence and avoid premature stagnation, adaptive parameter tuning, chaotic mutation via a tent map, and an early stopping criterion are incorporated, ensuring a balance between exploration and exploitation without excessive computation. Results For complex nested geometries, the proposed Tent-MP-GA-BBO framework achieved a PE of 1 pixel, maintained SSIM values above 0.99, and reduced computational time by up to 40% compared with the MP-GA-BBO baseline, demonstrating superior contour fidelity and optimization efficiency. Conclusions The integrated mapping strategy effectively harmonizes global exploration and local refinement, delivering a markedly more precise and efficient solution for high-precision maskless lithography mask optimization.
Sub-10-nm spacings on a wafer can be obtained using phase reversal on the photomask in conjunction with the 0.55 numerical aperture extreme-ultraviolet lithography. These spacings are a result of the minimum aerial-image intensity that occurs at the boundary of a pi-phase shifter, which can be fabricated by depositing additional molybdenum-silicon bilayers on top of the standard 40 pairs on the mask blank and selectively removing the added bilayers by masking and reactive-ion etching. Our calculated results are confirmed by rigorous simulations.
Background: Lateral gate-all-around (LGAA) device architectures-including nanosheet and forksheet structures-are becoming the dominant transistor platforms for sub-3 nm technology nodes. These architectures introduce multiple buried features such as silicon-germanium (SiGe) layers, dielectric-wall voids, and channel-release interfaces, many of which lie beneath hard-mask or dummy-gate stacks in actual process flows. As a result, the need for subsurface metrology that can access these features prior to or without cross-sectioning has grown substantially. Aim: The aim is to isolate and evaluate the intrinsic subsurface-visibility capability of high-voltage critical-dimension scanning electron microscopy (HV CD-SEM). This study investigates its feasibility using nanosheet test structures intentionally prepared without upper hard-mask or dummy-gate layers. Approach: Three LGAA-relevant inspection targets were examined: (1) voids within dielectric walls, (2) SiGe lateral recess amounts, and (3) multilayer SiGe residues after channel release. HV CD-SEM images were acquired at elevated landing energies to enhance backscattered-electron (BSE) sensitivity to embedded features. Monte Carlo simulations were performed to interpret voltage-dependent BSE signatures, and selected features were verified by transmission electron microscopy (TEM) or energy-dispersive X-ray spectroscopy (EDX). Results: HV CD-SEM successfully visualized dielectric-wall voids, extracted SiGe recess amounts using SE/BSE paired contrast, and detected SiGe residues originating from distinct depths within the nanosheet stack. Recess extraction was applied at 163 sampling locations, enabling wafer-level evaluation of layout-dependent micro-loading effects, whereas TEM cross-sections provided limited but essential reference values. Simulations correctly predicted the voltage-dependent detectability of multilayer SiGe residues, and EDX confirmed Ge-related contrast in the HV CD-SEM images. Conclusions: These results show that HV CD-SEM possesses intrinsic subsurface-visibility capability when upper hard-mask and dummy-gate layers are absent, demonstrating feasibility for detecting voids, SiGe recess profiles, and multilayer SiGe residues in nanosheet structures. Extending this approach to fully processed LGAA devices-where upper gate-stack layers remain in place-represents an essentially next step toward establishing HV CD-SEM as a comprehensive inline subsurface metrology technique.
