This paper presents a simulation based approach to decompose the overall conducted RF emission of a complex integrated circuit (IC) into partial emission spectra due to various functional blocks or processes in the analyzed DUT IC. The approach is described based on a generic power switch.
This paper reports the functional behavior of a system consisting of a pressure sensor within its sensor module, a two-wire supply with current modulated communication channel and an electronic control unit equivalent during powered system-level ESD tests. It discusses functional recoverable soft-failures, their failure mechanisms and root causes considering overall system properties as well as special electro-mechanical integrated circuit properties, and ESD test requirement and procedures.
This paper presents a method for determining the appropriate sensing resistance value when measuring integrated circuit (IC) noise in DC-DC converter ICs using the 1 Omega method as outlined in IEC 61967-4. By modeling the DC-DC converter circuit as an equivalent RLC resonance loop and accounting for the parasitic inductance of the sensing resistor, we established the permissible range for the sensing resistance. Through circuit simulations, this study examines the impact of sensing resistance and parasitic inductance on the ringing noise of DC-DC converter ICs, ultimately determining the optimal resistance value for accurate IC-level noise measurement.
Introducing a new high-speed design requires a careful optimization of any discontinuities that may degrade signal quality. A high-speed signal includes structures such as BGA (Ball Grid Array), vias, AC coupling capacitors, or connectors. Poorly matched impedance may result in undesirable signal reflections, energy losses, and electromagnetic interference. These structures need to be wisely optimized in order to limit signal reflections along the path while taking into account manufacturing constraints, costs, performance and routing density for avionics products. However, with each new design change during the various stages of development, major modifications can challenge previous optimization choices. Therefore, it is crucial to create adaptive and flexible models that can easily evolve with these changes. The objective is to develop a library of optimized models that can be seamlessly integrated into internal routing tools and efficiently reused for future designs. Three types of mathematical algorithms were studied based on the objectives, constraints, performance, and time required to converge toward the best design in order to automate this time-consuming process.
To analyze IC destruction and malfunction due to ESD (IEC61000-4-2), we proposed an on-chip current sensor that can accurately capture the entire ESD current waveform flowing into the IC that oscillates significantly for positive and negative in the nanosecond range. Measurement accuracy has improved by compensating for measurement errors caused by voltage overshoot in the nanosecond range of the current detection device. The ESD current waveform flowing into the IC is different from the standardization waveform, and a positive and negative oscillation waveform can come in, and we have designed to handle these polarities. This sensor sets a design window that does not incorrectly respond against noise that does not affect the system, and it only captures ESD currents of ampere or more. This sensor will become an important component for analyzing IC destruction and malfunction due to ESD.
