We propose a battery-aware multi-trip drone routing framework for post-disaster delivery that considers the mixed criticality of supplies under deadline and energy constraints. In this framework, each delivery request is assigned a criticality level and a delivery deadline, and drones are allowed to switch to a high-speed flight mode for urgent deliveries at the cost of increased energy consumption. The proposed optimization model simultaneously determines the number of drones, the delivery routes, and the flight speed mode for each segment, enabling a trade-off between energy consumption and urgency. Low-criticality deliveries may be skipped to prioritize highcriticality ones. Experimental results show that the proposed method improves the on-time delivery success rate for highcriticality items from 59.2 % to 89.3 %, compared to a baseline. In addition, the delivery rate for low-criticality items also slightly increases from 38.6% to 45.3%, supported by the increased number of drones. These results demonstrate the effectiveness of criticality-aware planning and provide insights into how to allocate and configure drone fleets for effective disaster response logistics.
This paper addresses the deadline-constrained task offloading and resource allocation problem in multi-access edge computing. We aim to determine where each task is offloaded and processed, as well as corresponding communication and computation resource allocations, to maximize the total saved energy for IoT devices, while considering task deadline and system resource constraints. Especially, our system allows each task to be offloaded to one of its accessible access points (APs) and processed on a server that is not co-located with its offloading AP. We formulate this problem as an Integer Nonlinear Programming problem and show it is NP-Hard. To address this problem, we propose a Graph-Matching-based Approximation Algorithm (GMA), the first approximation algorithm of its kind. GMA leverages linear relaxation, tripartite graph construction, and a Linear Programming rounding technique. We prove that GMA is a 1 - alpha/2 + epsilon approximation algorithm, where epsilon is a small positive value, and alpha (0 <= alpha < 1) is a system parameter that ensures the resource allocated to any task by an AP or a server cannot exceed alpha times its resource capacity. Experiments show that, in practice, GMA's energy saving achieves 97% of the optimal value on average.
Autonomous systems, such as autonomous vehicles and robots, typically use middleware like Robot Operating System (ROS) to manage communication, execution, and functionality. These systems sample sensing data at fixed rates from various sources and propagate it among independently developed tasks using a publish-subscribe scheme. A common issue is the nature of dynamic fluctuations in task execution time for processing this data, exacerbated by resource contention, dynamic environments, and scheduling strategies. This dynamism, combined with the lack of runtime coordination of task execution at the operating system level, leads to misaligned task execution rates, which is undetected by both middleware and operating systems. As a result, this misalignment (i.e., uncoordinated task execution) causes message drops, resource wastage, and degraded realtime performance. To address these challenges, we propose an Adaptive Task Execution rate Regulation (ATER) framework specifically designed for ROS 2-based systems. ATER consists of two key components: a runtime observer and a task regulator. It seamlessly integrates with the ROS 2 system without affecting its execution or requiring any modifications to its source code. By adapting the sensor data sampling rates at runtime, our framework effectively enhances the real-time performance of ROS 2-based systems through reduced message drops, efficient utilization of computational resources, and improved end-to-end latency.
We design and develop EtherTime, a tool for empirical evaluation of open-source implementations of the widely adopted Precision Time Protocol and Network Time Protocol standards. EtherTime is designed for distributed embedded systems networked over Ethernet. To demonstrate its benefits, we assemble a testbed of Raspberry Pi 4/5, Xilinx ZUBoard 1CG, and NVIDIA Jetson TK-1 boards, and carry out a measurement-based evaluation of four popular open-source implementations — PTPd, LinuxPTP, SPTP, and Chrony. EtherTime is successful in highlighting their limitations with regards to resource contention (specifically network and memory) and faults of various kinds (with/without hardware clock support). We open-source EtherTime and all datasets derived from this empirical study.
Nowadays, many functionalities are integrated in embedded real-time systems, leading to an increase in the number of their software and hardware components. In this context, the interest in mixed-criticality scheduling is growing [1].
Real-time cardiovascular disease (CVD) detection on wearable devices presents significant challenges due to the varying heart rate conditions and constrained computational capabilities of embedded systems. Existing approaches often struggle to balance diagnostic accuracy with the strict latency requirements imposed by different heart rate scenarios. In this study, we propose an Adaptive Model Selection (AMS) framework coupled with an anytime Convolutional Neural Network that integrates Residual Blocks, Squeeze-and-Excitation layers, and a Global Attention mechanism. By dynamically adjusting the model's complexity based on real-time heart rate, our solution optimizes diagnostic accuracy while ensuring a timely response. Evaluations conducted with the PhysioNet Database on a Raspberry Pi 4 demonstrate that our model achieves an accuracy of 91.5% with an average inference latency of only 1.33 ms per sample. These outcomes illustrate the effectiveness and practical applicability of our framework for robust, responsive, and accurate on-device ECG monitoring in continuous cardiac care. Our code is available online on GitHub(1).
This paper considers non-clairvoyant scheduling with predictions to minimize total completion time, with a focus on the often-overlooked impact of prediction costs. Prior works assume ideal settings where predictions are cost-free at inference, but quality predictions require time, which is critical when optimizing a time-sensitive metric. We investigate the trade-off between prediction accuracy and inference time in learning-augmented scheduling by simulating datasets with models of varying accuracy and inference times. Using Gaussian Processes to model this relationship, we find that highly accurate predictions with long inference times are suboptimal, whereas moderately accurate models with fast inference times yield empirically optimal performance.
Data-intensive applications benefit from offloading data processing to storage devices with embedded cores, typically Computational Storage Device (CSD). Co-locating requests from different applications to one CSD offers better performance and power efficiency than dedicating CSDs to a single application. However, current CSD scheduling frameworks fail to handle the contention in CPU, Flash I/O and buffer due to mismatching of resources and the requests, leading to sub-optimal performance. This paper proposes REMUS, a CSD scheduling framework handling multiple requests for CSD platforms with multiple homogeneous cores. The key idea of REMUS is to allocate the workload to multiple cores according to the distribution of the Logical Block Address (LBA) of the requests and mitigate stall time by sorting requests based on their urgency of demand for resources, where urgency is quantified by the current remaining buffer capacity of the requests. Furthermore, a buffer allocation scheme is proposed to avoid programs that exclusively occupy the resources. We conduct experiments on both a simulator and a real CSD platform. The experiment results show that REMUS improved throughput by 1.51x on the simulator and 1.39x on the real platform on average compared to the baselines.
Ethernet communication technology is growing in deployments across many real-time embedded systems. Through the IEEE 802.1 standardization group, Ethernet has been enhanced with several protocols and traffic scheduling policies, commonly known as Time-Sensitive Networking (TSN). Timetriggered communication is a common approach in TSN, but unfortunately not able to meet timing constraints for applications with very stringent real-time requirements. Past work has addressed this issue by combining time-aware scheduling with frame preemption, another key TSN standard. While frame preemption enhances schedulability, it comes with additional hardware cost for endpoints and switches. To reconcile the requirements of low-cost, real-time applications, this paper addresses the joint problem of minimizing hardware preemption cost and scheduling real-time communications across packetswitched Ethernet networks. We propose a monolithic SMT solution as well as efficient heuristic approaches to minimize cost and synthesize preemptable time-triggered network schedules. The proposed approaches have been evaluated through extensive experiments.
Autonomous driving (AD) systems demand high computational power, leading to substantial carbon emissions from power usage. Beyond emissions related to power usage, embodied carbon from car-borne battery manufacturing is also a major concern. Repeated battery charging cycles accelerate capacity degradation, shorten battery lifespan, and ultimately necessitate battery replacement, which results in additional embodied carbon emissions. Moreover, battery degradation is affected by environmental factors such as ambient temperature and charging current, making it difficult to predict. To reduce both power usage and embodied carbon emissions, we propose LCAD, a low-carbon autonomous driving computing system via adaptive solar battery systems. LCAD harvests solar energy to reduce carbon emissions from fossil power usage. To mitigate embodied carbon from battery degradation, it dynamically switches the car-borne battery between solar charging and non-charging options. However, achieving optimal switching is challenging due to intricate interdependencies among factors such as temperature variations and fluctuating solar energy availability. To this end, we employ deep reinforcement learning (DRL) to learn an optimal switching policy. Real-world tracedriven simulation results demonstrate that LCAD significantly reduces overall carbon emissions compared with the conventional design without solar energy and battery and the other battery charging control approaches.
Real-time cyber-physical systems (CPS) are increasingly deployed in command and control applications for safetyand mission-critical domains such as autonomous vehicles and critical infrastructure. To enable enhanced capabilities, CPS are becoming more complex and interconnected, yet this expanded functionality introduces new security vulnerabilities. Addressing these challenges, this paper presents a secure and resilient scheduling technique for hard real-time CPS applications that protects against common memory-corruption-based attacks. Our approach introduces a security-oriented dimension of criticality, enabling the system to selectively drop low-security-critical workloads in response to detected threats. This reduces the attack surface and allows for the timely rescheduling of both victim task re-executions and system recovery processes. We demonstrate that traditional mixed-criticality scheduling approaches are overly conservative and inadequate for accommodating dynamic recovery requirements under this security model. To address this, we propose a novel scheduling algorithm tailored for securityaware CPS, along with a schedulability test using a securitycriticality demand-bound function. The proposed framework is implemented in FreeRTOS with micro-ROS and validated using a hardware-in-the-loop simulation of a flight control task. Extensive schedulability experiments reveal that our model outperforms existing approaches with required adaptation, improving acceptance ratios by over 30 percent in heavily utilized CPS environments. This work advances secure, real-time scheduling to enhance both the resilience and safety of critical cyber-physical applications.
Lane merging is a common cause of traffic congestion and delays. The advancement of connected and autonomous vehicles can address the problem and improve the traffic efficiency. In this paper, we aim to schedule the passing order of vehicles in a three-to-two lane-merging problem and minimize the time needed for all vehicles to pass the merging intersection. We propose a three-dimensional dynamic-programming-based algorithm to solve the problem. We introduce a groupingbased strategy to reduce the computational overhead. The experimental results and SUMO simulation show that the threedimensional dynamic-programming-based algorithm achieves a comparable solution quality in much less time than an optimal approach based on mixed integer linear programming. Besides, the grouping-based strategy makes the real-time computation applicable and achieves a balancing trade-off between computation time and solution quality. The dynamic-programming-based algorithm can be further generalized for solving any $n$-to- $(n-1)$ lane-merging problem.
Deep Learning (DL) models are typically deployed on high-computation platforms like GPUs and FPGAs in cloud environments, leading to high latency and network dependency. In contrast, performing deep learning inference on micro-controllers in automotive applications reduces latency, minimizes network dependency, enhances security, and offers a cost-effective solution. This paper investigates the integration of deep learning models into AUTOSAR-compliant C-code for automotive Electronic Control Units (ECUs). Adhering to AUTOSAR standards guarantees compatibility, scalability, maintainability, and efficient resource management. The study emphasizes toolchains that transform deep learning models, initially trained and developed in Python with frameworks such as TensorFlow or PyTorch, or using other tools like MATLAB, into high-quality AUTOSAR-compliant C-code, tailored for specific compilers and hardware optimizations. Upon deployment, the deep learning software module within the ECU must satisfy rigorous real-time system requirements. In this paper, we demonstrate the integration of a deep learning model into an ECU, emphasizing automation and seamless incorporation into existing workflows. The workflow setup can be extended to various deep learning models, but we use a simple neural network for estimating the battery's state of health to illustrate the process. The model is trained in Python, quantized for ECU deployment, and converted to AUTOSAR-compliant C-code through three methods: manual implementation with TargetLink, Simulink combined with the Deep Learning Toolbox, and a hybrid approach integrating Simulink-generated code into existing TargetLink logic using S-functions. This comparison focuses on fixed-point scaling and hardware optimization to ensure code efficiency, reliability, and correctness, verified through static code analysis and unit testing. Functional tests in a Software-in-the-Loop (SIL) environment validate system performance and accuracy by comparing results to a physics-based model. Hardware-in-the-Loop (HIL) testing assesses real-time behavior and robustness, ensuring reliable performance with actual hardware components under real-world conditions.
We propose an unsupervised machine learning approach for classifying cyberattacks on smart power grids, with a focus on multi-area AGC systems. Unlike prior work on attack design or detection, our method is the first to classify advanced attacks without labeled data. By analyzing internal gradients from a VAE combined with a TCN, we distinguish among time delay (TDA) and two types of false data injection (FDI) attacks. Simulations using PowerWorld show that K-means clustering on these gradients achieves over 95 % accuracy-comparable to supervised methods but without costly labeling. Our approach also detects zero-day attacks as distinct clusters using equilibrium K-Means.
Real-time Edge AI applications often require efficient GPU-based data processing and communication. Since the applications are typically highly modularized, publish-subscribe (pub/sub) pattern is widely used to deliver data among components. However, existing pub/sub middleware introduces significant latency due to redundant memory copies between GPU and host memory. To address this, we propose GPU-Aware Pub/Sub communication (GAPS), a universal solution that integrates shared CUDA memory with existing pub/sub middleware, such as Zenoh-pico and Iceoryx. GAPS minimizes data transfer latency by enabling GPU memory sharing between publishers and subscribers, eliminating unnecessary memory copies. In our work, we propose an independent shared CUDA memory manager that creates a shared CUDA memory pool for each topic during a topic's initialization. For fine-grained allocation from the pool, we modify Two-Level Segregated Fit (TLSF), a real-time dynamic memory allocator, making it process-safe and capable of managing GPU memory. Additionally, we develop PyGAPS, an extension that accelerates publications of PyTorch tensors, eliminating serialization overhead in AI-driven applications. Our evaluation demonstrates that GAPS significantly reduces end-to-end latency and improves throughput of simplified computer vision pipelines-by up to 1.5x in the segmentation task and 3.8x in the classification task-making it a robust solution for real-time Edge AI.
Urban firefighting faces significant challenges in acquiring temperature data within complex building structures during rapid urbanization. The Surefire UAV testbed was developed to address this challenge. The testbed leverages an unmanned aerial vehicle (UAV) equipped with a spherical sensor, capable of being deployed at designated target points to collect temperature data. This testbed is a typical Cyber-Physical System (CPS) testbed, integrating both the cyber components (flight control software and sensor deployment software) and physical components (UAV hardware, sensors, motors, etc.).
Modern real-time embedded systems increasingly rely on Arm-based Multiprocessor System-on-Chip (MPSoC) architectures to support demanding applications, such as AI workloads and high-speed control systems. To mitigate interference among co-running applications and enforce predictable behavior, software memory bandwidth regulation strategies based on hardware performance counters have been proposed to manage concurrent memory accesses among CPUs. However, such mechanisms (e.g., MemGuard, MemPol) have been mostly evaluated on previous generations of 64-bit Arm systems, i.e., Cortex-A53, A57, or A72. Newer Arm MPSoCs, featuring clusters of Cortex-A55, A76, and A78 cores, introduce (i) the Arm DynamIQ Shared Unit (DSU), (ii) additional cache levels, and (iii) new memory controllers optimized to manage high-bandwidth transactions from accelerators (e.g., GPUs, TPUs). Extending software-based memory bandwidth regulation strategies to newer Arm cores is non-trivial and requires careful characterization of the newly introduced performance counters and the achievable worst-case memory bandwidth (sustainable memory bandwidth). This paper systematically investigates software-based memory bandwidth regulation on DSU-equipped Arm MPSoCs, using the Rockchip RK3588 and NVIDIA AGX Orin as two representative platforms. We empirically evaluate the impact of the new memory hierarchy on sustainable memory bandwidth and the accuracy of performance monitoring counters. We derive updated memory bandwidth regulation models and assess their behavior when applied to MemGuard and MemPol. Our results show that software-based memory bandwidth regulation strategies can be successfully applied to newer platforms. However, the different selection of performance counters might result in pessimistic regulation models.
Embedded real-time systems are increasingly turning to GPU-based SoCs to efficiently handle machine learning tasks at the edge. Modern GPU SoCs often feature specialized AI accelerators to enable concurrent CNN inference while maintaining energy efficiency. While this trend typically leads to a general improvement in performance, the integration of multiple AI accelerators presents challenges for building real-time systems, where ensuring timing predictability is a key design goal. On one hand, contention among various computation units over shared memory can introduce non-deterministic timing behaviors. On the other hand, the built-in GPU scheduling mechanism cannot assure that emergent tasks to be executed first, potentially violating real-time constraints. To tackle these challenges, this study introduces a timing predictability-aware cache locking policy to reduce main memory access volume and mitigate main memory contention with AI accelerators. Additionally, a real-time scheduling framework is proposed to bypass the inherent GPU scheduling algorithm.
The satisfiability (SAT) problem is one of the most fundamental NP-complete problems, and competitions for SAT solvers are held annually to benchmark solver performance. Accurate real-time prediction of solver runtime has become more important for optimal solver selection and efficient resource allocation, especially as solvers and hardware advance. In this work, we evaluate the performance of major machine learning models on SAT runtime prediction tasks, using recent SAT competition datasets. Furthermore, we use not only conventional evaluation metrics e.g., Root Mean Squared Error (RMSE) and Mean Absolute Error (MAE), but also more detailed metrics e.g., classification-based confusion matrices and cumulative error distributions. Consequently, we observe that the performance of random forest models, often showing the highest performance in previous studies, is poor and biased toward the median runtime, while the performance of Multilayer Perceptron (MLP) models is more robust even when their RMSE and MAE are higher. These results offer new insights not only for developing more reliable runtime prediction models but also for improving algorithm selection and resource management methods in SAT solving.
Cyber-physical systems are getting increasingly connected to cellular and wireless networks. As a prominent example, the automotive industry has witnessed a rapid increase in embedded software and electronics, and lately also increased connectivity to cellular communication networks. This trend enables the deployment of applications on network edge computers, offering opportunities for reduced embedded hardware footprint and increased expandability of new applications. Put differently, the traditional automotive platform comprising embedded networked processors expands to the cellular network and edge computing services in its environment. For real-time applications, which are very common in the automotive domain, the aforementioned trend gives rise to completely new challenges in that mobility and the underlying cellular network impact the temporal properties and the design and implementation decisions of the application. In this paper, we address the problem of synthesizing task allocation of real-time applications in the embedded-edge compute continuum, with key considerations for mobility and minimization of embedded compute utilization. We present an exact SMT-based solution as well as efficient heuristics with extensive experimental evaluations.
