Modern clustered (power-island) multicore processors increasingly expose retention as a low-overhead low-power state, yet exploiting it in real-time systems critically depends on whether the scheduler can create sufficiently long cluster-level all-cores-idle windows that exceed a break-even length. This feasibility bottleneck is particularly acute for always-on arbitrary-deadline Directed Acyclic Graph (DAG) workloads, where precedence-induced execution fluctuations fragment idle times and the relative deadline may exceed the period. This paper proposes a retention-oriented scheduling framework for such workloads, consisting of two algorithms with a clear progression. PRES performs design-time planning and constructs a postponable division for each DAG, reshaping execution to aggregate slack into contiguous cluster-level idle windows; a lightweight event-driven runtime then enforces the plan and triggers retention without increasing online scheduling complexity. Building on PRES, PREHS further improves core utilization via multi-DAG merging and intra-cluster spatial sharing, consolidating workload onto fewer active clusters to reduce static/leakage energy while preserving deadline guarantees. We conduct extensive experiments across diverse cluster configurations and DAG structural characteristics, and further include a case study based on an application-derived DAG from a real-world communication/signal-processing pipeline. The results show that, compared with a representative work-conserving baseline with automatic retention/PG, PREHS reduces static energy consumption by up to 65.62%; moreover, under the same resource constraints, PREHS improves task acceptance ratio over PRES by up to 43 percentage points, with the largest gains observed in resource-tight configurations.
Autonomous vehicles at L2 and above are increasingly relying on stereo vision systems, where haze removal is critical to detect obstacles hidden in fog. Existing image haze removal techniques have low processing speed and high resource consumption, restricting their application scope in practice. In this work, we propose a hardware-software co-design solution for haze removal. It fully decouples the calculation of the two main parameters, i.e., atmospheric light and transmission, in the dehazing process. By eliminating the data dependency, parallelism in hardware acceleration is enhanced. Furthermore, in replacement of the conventional global homogeneous atmospheric light computation, we report a chunk-based heterogeneous method to reduce cache overhead. Our approach is implemented on both GPU and FPGA, compared against six state-of-the-art (SOTA) works for image haze removal. Evaluation using test sets of real-world foggy driving scenarios shows that our object detection accuracy is over 88%, 9.5%-47.4% better than the SOTA works with neural networks (NN) on GPU, 42.2% better than the non-NN SOTA on GPU, and 25.9%-52.2% better than the SOTA works on FPGA. The processing speed varies with image resolution and our improvement is generally even more at higher resolution. In FPGA implementation, our approach is 29.7% faster than the fastest SOTA at the lowest resolution of 360p. We have the lowest overall resource consumption, where the bottleneck BRAM usage is reduced by over 70%. In GPU implementation, our approach is 2-3 orders of magnitude faster than the NN-based SOTA works, and saves two orders of magnitude in memory, from about 10GB to hundreds of MB. The non-NN SOTA on GPU also consumes hundreds of MB in memory, and we are 31.4% to 66.5% faster than it, at different resolutions. Our power consumption is 5.7W and 53W, the lowest in the FPGA and GPU category, respectively. To compare between ourselves in timing, both take several milliseconds. The GPU solution is slightly faster and more scalable, yet with fluctuation of -5.3% to +22.2%. The FPGA solution has circuit-level timing determinism at nanosecond, hence suitable for hard real-time applications.
Control flow errors (CFEs) pose a serious threat to the reliability of embedded systems, particularly under increasing integration density and shrinking feature sizes. Existing CFE detection techniques typically rely on coarse-grained analysis and uniform checking strategies, lacking fine-grained awareness of structural and runtime characteristics. This limitation often leads to considerable overhead, making such approaches less suitable for resource-constrained embedded systems. To tackle this shortcoming, we propose a CFE Detection approach guided by Basic block Vulnerability Analysis (CDBVA) that aims to strike a balance between the detection effectiveness and the overhead. Specifically, we first extract the CFE-related structural and execution features to characterize basic block vulnerability. Then, we train a learning-based model to predict basic blocks that are vulnerable to CFEs. Finally, we design a hybrid signature checking strategy that performs appropriate checks on vulnerable and non-vulnerable basic blocks separately. Experimental results demonstrate that CDBVA achieves an average prediction accuracy of 86.2% and an average CFE coverage of 95.79%, outperforming state-of-the-art approaches. While maintaining high CFE coverage, CDBVA improves the evaluation factor by 12.14%–20.82%, achieving a favorable tradeoff between detection effectiveness and overhead. In addition, CDBVA demonstrates stable performance across diverse input conditions and heterogeneous hardware architectures.
As cyberattacks on mobile networks become increasingly sophisticated, particularly SIM-based threats like SIM swap fraud and cloning, there is a critical need for robust, hardware-rooted authentication mechanisms. This article introduces SafeSIM, a novel authentication framework aimed at enhancing SIM card security in mobile environments. Unlike traditional schemes that rely on fixed identifiers and shared secrets, such as the International Mobile Subscriber Identity (IMSI), which uniquely identifies users, and the Authentication Key ( Ki ), used to verify their identity, SafeSIM employs dynamic, privacy-preserving Zero-Knowledge Protocols (ZKPs) and hardware-anchored Physical Unclonable Functions (PUFs), specifically VIA PUFs, embedded in SIM cards to ensure hardware-level uniqueness and robust resistance to cloning and fraud. The choice of VIA PUF is intentional, as VIA PUFs are more suited to constrained environments such as SIM cards due to their compact design and simplicity of integration. The authentication protocol is designed to operate securely in both trusted and untrusted service provider environments. In adversarial scenarios, SafeSIM integrates a two-factor authentication mechanism combining biometric verification with ZKP-based authentication for scenarios involving untrusted service providers, thereby offering heightened protection even in adversarial environments. We have analyzed the security of the proposed scheme in detail, alongside practical implementation using an Android mobile application, demonstrating strong resilience against a wide range of cyberattacks. These results position SafeSIM as a scalable and secure solution for next-generation mobile network deployments.
Edge Artificial Intelligence (AI) allows machine learning models to run directly on resource-constrained IoT and edge devices instead of relying only on cloud resources. This shift reduces latency and improves privacy but introduces strict constraints on memory, energy, and connectivity across heterogeneous sensor nodes. Deploying AI on constrained devices also requires addressing fragmented toolchains and inconsistent evaluation practices. This survey provides a structured review of deployment methods for edge AI, including model compilation, intermediate representations, hardware-aware optimization, scheduling strategies, and connectivity-aware execution. Post-deployment aspects are also examined, including lifecycle management, secure over-the-air updates, and benchmarking frameworks that combine latency, accuracy, and energy. Use cases in healthcare, smart cities, autonomous systems, manufacturing, and agriculture illustrate practical applications. Across these areas, common challenges in portability, reproducibility, adaptivity, and security are identified, along with emerging directions such as dynamic orchestration across heterogeneous devices and modular update mechanisms. By combining perspectives from compiler design, system optimization, and lifecycle management, this survey highlights how deployment pipelines are evolving into key enablers for reliable and scalable intelligence at the network edge.
Transformer-based Large Language Models (LLMs) have made significant progress in the fields of computer vision and natural language processing. The use of LLMs in embedded and real-time systems to provide more powerful intelligence capabilities is also an inevitable trend. However, the traditional von Neumann architecture encounters great challenges with transformer-based LLMs due to huge data movement overheads. Processing-in-Memory (PIM) emerges as a great potential solution by significantly closing the gap between computation and storage. Nevertheless, transformer-based LLMs usually consist of multiple transformer blocks, and the operations within each transformer block vary significantly on computation and memory access characteristics. Existing PIM designs that rely solely on SRAM, DRAM, or ReRAM cannot adapt well to transformer-based LLMs. To address these challenges, we introduce HyPIM, a 3D hybrid PIM architecture that integrates SRAM and ReRAM slices to process through their cooperation. However, HyPIM does not change the scenario where the inference latency of the attention mechanism continues to dominate the overall inference latency in the transformer-based LLMs when dealing with long sequences of data. Exploiting these insights, we then design a hardware-friendly early termination approximation algorithm and a sparse matrix multiplication strategy for the HyPIM architecture, reducing the overhead through a software and hardware co-design. Compared with the state-of-the-art Newton, TransPIM, HAIMA, HARDSEA, and H3DAtten architectures, the proposed HyPIM architecture achieves up to a 1.27×–1.67× latency improvement.
Cyber-physical systems (CPS) play a pivotal role in industrial automation, transportation, and critical infrastructure, where meeting stringent timing constraints is essential to ensure operational safety and efficiency. While reinforcement learning (RL) has shown promise in synthesizing controllers for time-critical applications, existing approaches often prioritize speed (as soon as possible, or ASAP) without explicitly addressing deadline compliance. This misalignment can lead to unsafe or suboptimal behaviors, which are unacceptable in industrial contexts requiring both safety and reliability under hard deadlines. For example, with inappropriate rewards, a control policy for a industrial robot can be encouraged to be less safe but fast instead of being steady and meeting the deadlines. To address this challenge, we investigate the relationship between ASAP behavior and deadline-safe behavior, introducing a novel Markov decision process formulation (R-MDP) that includes time-awareness while preserving the Markov property. We propose a reward design method that systematically encourages deadline compliance and guarantees safety in reach-avoid tasks. Our approach is validated on multiple benchmarks, including linear and nonlinear systems representative of industrial applications, such as DC motor control and real-time attitude control. Experimental results demonstrate the efficacy of our method in achieving deadline-safe control while maintaining system safety, offering a reliable solution for industrial CPS where failure to meet deadlines can have severe consequences.
Heterogeneous computing has emerged as a key paradigm for improving performance and energy efficiency. While fully customized accelerators achieve the best results in the applications for which they are designed, in terms of performance and energy efficiency, programmable accelerators strike a balance between these gains and applicability to multiple application domains. However, such systems are inherently hard to program. They are often programmed using imperative languages through low-level programming interfaces, requiring deep knowledge of the underlying architectural details. For domain scientists who could make the most use of the processing power available in such systems, the lack of abstraction in the programming model renders the learning curves unnecessarily steep. In this paper, we address the problem of programmability for heterogeneous embedded systems with programmable accelerators by systematically extending the domain-specific programming language Rise and its compiler Shine for an exemplary edge computing heterogeneous platform (PULP). Ultimately, Rise enables the programmer to express a problem in terms of what is being computed, while Shine optimizes the expression and compiles it to the language native to the target platform. We evaluated our approach against the native programming model (C) of our test platform as well as against other prominent solutions targeting embedded heterogeneous hardware. Our results show performance comparable to competing approaches while offering a cleaner and more concise programming model.
Light field image depth estimation methods involve a large number of parameters and floating-point operations. This makes FPGA-based acceleration design a huge challenge, especially when pursuing high-precision acceleration design on resource-limited FPGAs. Motivated by this issue, a resource-efficient hardware accelerator based on a high-precision, low-bit lightweight light field image depth estimation network scheme is proposed, named RE-LFDE. First, we present a parameter-sharing, low-bit and lightweight network. It is able to improve accuracy, simplify the network structure and reduce network parameters. Secondly, we design a time-division multiplexing hardware-software co-design dataflow structure and build a resource-efficient acceleration engine, which can be deployed on the resource-limited FPGAs efficiently. Experimental results show that the average MSE on the 4D LF benchmark of RE-LFDE and its full-precision networks can be reduced to 3.265 and 3.363, respectively, while the weight parameters can be as low as 0.30MB and 0.04MB. Furthermore, on the ZCU104 platform, the consumption of BRAM and LUTRAM can be reduced to 22.44% and 13.64%, respectively. The code and model of the proposed method are available at https://github.com/sansi-zhang/RE-LFDE .
The proliferation of Artificial Intelligence (AI) applications has driven a substantial demand for deploying Neural Networks (NNs) across a wide range of device platforms. Modern networks have become so computationally intensive that even relatively simple Convolution Neural Networks (CNNs) often require costly specialized hardware for efficient execution. To mitigate this challenge, techniques that distribute inference workloads across interconnected, resource-constrained devices have become increasingly important. While existing approaches typically rely on empirical models or support only limited partitioning dimensions, we introduce ADaPS-FC, a novel framework for optimally distributing CNN inference workloads across heterogeneous embedded devices. Our analytical model partitions the height, width, and channel dimensions of 4D CNN tensors while also exploring partition configurations that enable layer fusion. In addition, it introduces weight-division strategies for fully connected layers and small output operators to improve both memory usage and latency, fully accounting for each device’s computational capabilities and inter-device communication overhead. This work extends the previously proposed ADaPS method by addressing the limitations encountered in the later, non-divisible layers of CNN models. To efficiently navigate the large search space of possible partitionings, ADaPS-FC employs a hybrid optimization algorithm that combines Alpha–Beta pruning with dynamic programming for the earlier layers, where height or width division is feasible. For the later layers, where the prior method was unable to apply spatial partitioning, the framework introducess weight (channel) division to enable further distribution opportunities. We evaluate ADaPS-FC across multiple CNN architectures deployed on interconnected heterogeneous hardware, using configurations ranging from two to four devices. Experimental results show that ADaPS-FC improves inference time by 1.3 × on average over previous state-of-the-art.
The optimization of Deep Neural Networks (DNNs) for resource-constrained environments through quantization and pruning necessitates efficient re-verification to ensure safety. However, existing incremental verification methods are primarily designed for numerical parameter perturbations and often struggle to handle the discrete structural changes introduced by network pruning. Moreover, traditional approaches verify each model variant from scratch, discarding the significant computational effort invested in the original model’s proof. In this paper, we present MUC-G4 , an incremental verification framework that accelerates the certification of compressed DNNs via search space pruning. Inspired by the principles of residual reasoning and conflict-driven learning , MUC-G4 identifies Minimal UNSAT Cores (MUCs) as robust proof artifacts that capture the local logical reasons for safety. Our work is grounded in the insight of Locality of Conflicts : the logical contradictions that guarantee safety are often independent of the redundant neurons and connections targeted by compression algorithms. MUC-G4 extracts these MUCs from the original network’s proof and utilizes them as a warm-start mechanism to identify and prune stable infeasible regions in the compressed network’s search space. Experimental results on the ACAS Xu and MNIST benchmarks demonstrate that safety proofs exhibit high structural resilience. Crucially, the framework maintains full completeness through a residual solving phase, ensuring that all newly exposed search paths are rigorously verified. Our findings suggest that formal proofs can effectively evolve alongside optimized network variants, providing a scalable foundation for the continuous certification of safety-critical machine learning systems.
Embedded object detection systems demand 2D convolution hardware modules that consume less processing and storage resources and process frames in high performance and high resolution. Existing solutions address performance, resource, and accuracy issues isolatedly. This work introduces resource optimization strategies for processing 2D convolution modules, such as temporal and spatial memory sharing between kernel units. This work proposes a new strategy for aligning weights between units using rotational displacement, which allows the division of the same memory into several kernel units. In a case study of pedestrian detection based on support vector machine (SVM), the proposed solution reduced the amount of memory, logical elements, and registers by more than half compared to non-optimized solutions. The proposed strategies achieved significant results using the image pyramid, decreasing almost a quarter of the overall resources. The new proposed strategy did not reduce the detector’s performance since it did not interrupt the processing flow. The proposed solution reached 14 levels of the image pyramid and full HD resolution, with results in accuracy, processing performance, resource occupancy, and power dissipation higher than existing SVM-based pedestrian detectors. Adopting these strategies can provide promising results in embedded deep-learning models.
Today’s embedded microcontrollers (MCUs) are designed to achieve both timing predictability and low energy consumption. This is usually done by using features that trade energy savings for faster execution ( e.g., DVFS or prefetcher) and the ones that can improve both time and energy performance but are limited in size ( e.g., core-coupled memories and caches). In this paper, we evaluate the impact of core-coupled memories in this regard on the example of two low-powered embedded MCUs, each with a different level of hardware support. Our study reveals the importance of core-coupled memory allocation for both timing and energy performances. The performance gains are particularly significant on simple devices where DVFS and caches are not available. We formulate a memory allocation problem using integer linear programming to minimize power consumption under timing and memory constraints. We also propose a heuristic with quadratic time complexity in the number of tasks to solve the allocation problem. The evaluation based on real-world benchmarks and a case study demonstrates an energy consumption reduction of 10-20% when compared to the default MCU configuration ( i.e., maximal CPU frequency and program’s code in Flash).
With the advancement of heterogeneous computing technique, efficient model inferences designed for various domains have been successfully developed upon real-time embedded platforms. For those applications (e.g., drones and autonomous driving) demanding both highly parallel computation via Graphics Processing Units (GPUs) and strict timeliness constraints, effective scheduling of real-time activities upon heterogeneous systems remains challenging. With the intrinsic and intricate interferences among tasks (contending for the GPU resources) being considered, we first investigate two resource-cognizant utilization bounds for partitioned-EDF (Earliest Deadline First) scheduling under suspension-oblivious (i.e., busy-waiting) paradigm, and then explore their non-monotonicities. Based on the insights gained from the bounds, we further propose SP-RA-TMA (Spatial-Partitioning and Resource-Aware Task Mapping Algorithm) for periodic tasks executing upon CPU-GPU systems. Specifically, several blocking-oriented approaches for appropriate vGPU-to-core partition and feasible task-to-core mapping are introduced, in order to tighten the bound of blocking overheads for tasks and effectively alleviate the negative effects of GPU resource competitions for better schedulability of task set and balanced system workload. Finally, the synthetic and empirical experiment results demonstrate the practicability of SP-RA-TMA that can achieve a higher acceptance ratio (e.g., 80% more) compared to the existing partitioned/dynamic schemes.
In recent years, deep learning side-channel analysis (DLSCA) has garnered significant attention, with the choice of model architecture greatly influencing attack efficiency. Currently, convolutional neural networks (CNNs) have become the dominant architecture in the field of side-channel analysis (SCA), and multi-scale CNNs (MCNNs) have gained favor among certain researchers due to their ability to capture information across various scales. However, effectively obtaining multi-scale information from datasets requires the customization of appropriate hyperparameters for each channel, and the hyperparameter tuning process is often time-consuming and labor-intensive. This presents a technical barrier for non-experts or those seeking to simplify their workflow. Such limitations lead researchers to overly rely on fixed hyperparameter models based on specific datasets, overlooking the differences between various data samples, which in turn affects the model’s reusability and generalization capability in broader scenarios. To address these issues, we propose an adaptive MCNN framework based on automated machine learning, named Auto-MCNN. We evaluated the effectiveness of this framework on multiple private and public datasets. To further investigate the variations in the network’s feature extraction capabilities, we employed an improved heatmap visualization method to illustrate the network’s areas of focus. Experimental results demonstrate that the optimized Auto-MCNN model can be more widely applied to the analysis of side-channel leakage traces, significantly enhancing overall analysis efficiency.
Wearable human activity recognition (HAR) focuses on classifying human activities from multi-sensor data collected by wearable devices and has become increasingly important in pervasive computing. However, existing methods face several challenges: (1) aggregating heterogeneous local models while preserving user-specific data distributions, (2) achieving personalized adaptation of global models to diverse behavioral patterns, and (3) capturing both local and global temporal dependencies inherent in sensor time-series data. To address these challenges, we propose PFLMamba, a personalized federated learning framework integrating an attention-enhanced state-space model (ASSM) for hierarchical temporal feature extraction. PFLMamba employs a server-side personalized attention aggregation mechanism to tailor global models for individual clients, while ASSM captures both local and long-range temporal patterns on the client side. Extensive evaluations on the WISDM and PAMAP2 datasets demonstrate that PFLMamba achieves F 1 scores of 91.83 and 96.01, respectively, outperforming state-of-the-art federated learning baselines such as FCLFD, EFDLS, and FKD. PFLMamba’s effectiveness is further validated on multi-user and heterogeneous-sensor datasets, namely UCI-HAR and UNIMIB-SHAR, confirming its generalization across diverse populations and device types. Beyond predictive accuracy, PFLMamba exhibits a favorable trade-off between efficiency and performance, with lower client-side training overhead than teacher-student-based frameworks and competitive throughput relative to lightweight alternatives. Further experiments on resource-constrained edge devices (i.e., Raspberry Pi 4 and PYNQ-Z2) validate its practical feasibility, highlighting low-latency inference and moderate energy consumption. These results establish PFLMamba as a robust and efficient solution for personalized wearable HAR.
Increasingly, machine learning inference is implemented on relatively low-powered edge devices, where battery life is a key performance criterion. In this work, we demonstrate how C++20 coroutines can be used to reorganise the execution order of an iterative inference task on an edge device. A Prognostic and Health Management (PHM) application receives streams of vibration data as envelope spectra from a wireless sensor network and processes them locally through an array of Support Vector Machines. In our experiments on ARM Cortex A72 & A53 64-bit SoCs, this method can reduce energy consumption for the task by up to 18%, reduce overall energy use by up to 20% and cut execution time by up to 20.5%. Furthermore, peak power levels are reduced by up to 4.5%, which can increase battery lifespan by reducing wear. We demonstrate that the necessary changes to the C++ code are simple, repeatable and generally applicable to iterative inference tasks.
Many embedded applications have strict energy, memory, and time constraints, making neural network (NN) inference particularly challenging. Recently, a novel NN architecture, called Fast Feedforward Networks (FFFs), has been proposed to achieve inference with extremely lightweight computational demands and minimal latency. Yet, compared to feedforward networks with similar sizes, FFFs still lag behind in terms of performance, indicating that they do not utilize all of their parameters effectively. In this article, we explore a possible reason for this performance gap: the uncertainty in how samples are assigned to the network’s leaves. We attempt to overcome this challenge by making FFFs’ training inference-aware, hence introducing Inference-Aware Fast Feedforward Networks (IAFFFs). We imitate FFFs’ inference during training by using a step activation function alongside the traditional sigmoid activation function. We test different aware scheduling methods, which we dub “awareness scheduler”, to adjust the balance between the two activation functions during training, and examine how different schedules impact the model’s performance. Additionally, we employ leaf-weight virtualization with inference-aware retraining to compress our models so they can fit onto edge devices. We further employ an iterative compression approach to find an optimal awareness scheduler for compression to minimize performance drop due to compression. We experiment with different model sizes on various microcontrollers (MCUs) with different memory constraints to observe the latency and energy consumption introduced by the compression algorithm.
Dynamic Thermal Management (DTM) systems are critical to the reliable operation of Multiprocessor System-on-Chips (MPSoCs), yet remain vulnerable to sophisticated thermal manipulation attacks. These attacks, executed through hardware trojans or privilege escalation, can compromise the integrity of thermal sensors, causing performance degradation, accelerated aging, and catastrophic hardware failure by disabling thermal throttling mechanisms. Existing countermeasures rely on reactive detection methods and conventional machine learning models that fail to capture the complex physics governing thermal systems, including thermal coupling across cores and power-frequency interdependencies, making them ineffective against multi-stage attacks that exploit DTM decision-making logic. This work presents a novel transformer-based defense framework that leverages self-attention mechanisms to model rich, system-wide feature interactions for detecting adversarial thermal manipulations in real time. The proposed hybrid architecture integrates an adaptive pre-filtering with dynamic thresholding to achieve an 83x throughput improvement (22,798 samples/second versus 274.53 samples/second for transformer-only baseline) and nearly 50% lower GPU utilization, enabling deployment on resource-constrained embedded platforms. Comprehensive on-device validation on the NVIDIA Jetson AGX Orin board demonstrates substantial thermal regulation improvements, reducing average peak temperatures from 103 °C to 98.5 °C while maintaining a model active ratio of only 2.73%. The framework incorporates an adaptive defense system with load-dependent dynamic thresholding that achieves high F1-scores in detecting the thermal attacks discussed in the literature (0.75 to 0.9). This work bridges the critical gap between simulation-based security research and practical embedded system deployment, establishing a new paradigm for lightweight, attention-based anomaly detection in thermally constrained environments.
