Hierarchical storage systems in HPC environments combine a high-performance SSD tier with a high-capacity HDD tier, managed at file granularity by policy engines such as Robinhood. A widely used strategy in such systems is to promote on single access (OSA)—migrating any file on its first miss. While OSA maximizes hit ratio, it triggers expensive full file migration and causes SSD/HDD “churn” transfers under skewed access patterns, leading to SSD pollution by weakly reused files, unnecessary data movement, and degraded device endurance.This paper presents ORBIT, a file-level placement policy that couples selective admission with multi-criteria ARC-based eviction (MC-ARC). ORBIT admission controller maintains a lightweight, continuously aged usage score that is size-aware and sensitive to the accessed file fraction. When SSD space is needed, ORBIT relies on MC-ARC to evict files by aggregating ARC-derived recency/frequency with predicted remaining lifetime and per-user fairness.Trace-driven simulations on representative HPC workloads show that, compared to the MC-ARC baseline, ORBIT reduces costly data movement across SSD/HDD; the migration volume drops by 95.7%, SSD writes by 97.4% and mean access latency by 78.9%. Despite a lower hit ratio in some cases, avoiding non-profitable promotions yields large end-to-end gains, e.g. 70% average I/O-time reduction across the evaluated workloads and SSD sizes. These results highlight that, at file granularity, disciplined admission and multi-criteria eviction can outperform hit-centric strategies by minimizing migration-dominated overheads in multi-tier HPC storage.

Today’s space systems, such as the PLATO satellite, need to process a large amount of data in space, and therefore may use multi-core architectures. To improve timing predictability and reduce analysis complexity, they may use Asymmetric Multi-Processing (AMP), where each core has its own application and operating system.As cores can execute subsystems supported by different operating systems, the overall system implementation requires inter-core communications implemented through portable mechanisms. These communications might also have to meet timing constraints.In this article, we propose PrAICC (Predictable AMP Inter-Core Communication), a timing predictable inter-core communication model for multi-core heterogeneous AMP architectures. PrAICC has been designed to enforce schedulability while ensuring message latency requirements. It is based on shared memory and platform-agnostic spinlocks to ensure portability, and on polling for timing predictability. We also propose a method to assess the schedulability of applications communicating with PrAICC.Our evaluations showed that the schedulability model is able to predict message latencies and task worst-case response times. They also emphasized that the task worst-case response time is mainly due to spinlock waiting time and holding time. Furthermore, PrAICC performance is independent of the core count.The schedulability model of PrAICC is able to explore trade-offs between schedulability analysis pessimism and message latency. An evaluation based on the PLATO case study was conducted to validate the effectiveness of PrAICC. It determined that the best compromise between message latency and predictability is achieved with a polling period of 100 ms. We can note that this result is consistent with the choice previously made by the teams working on the operational requirements of the PLATO mission. With such a period, the message latency and the schedulability analysis pessimism are respectively bounded to 133ms and 48%.

Distributed data-centric systems, such as Named Data Networking, utilize in-network caching to reduce application latency by buffering relevant data in high-speed memory. However, the significant increase in data traffic makes expanding memory capacity prohibitively expensive. To address this challenge, integrating technologies like non-volatile memory and high-speed solid-state drives with dynamic random-access memory can form a cost-effective multi-tier cache system. Additionally, most existing caching policies focus on categorizing data based on recency and frequency, overlooking the varying Quality-of-Service (QoS) requirements of applications and customers—a concept supported by Service Level Agreements in various service delivery models, particularly in Cloud computing. One of the most prominent algorithms in caching policy literature is the Adaptive Replacement Cache (ARC), that uses recency and frequency lists but does not account for QoS. In this paper, we propose a QoS-aware Multi-tier Adaptive Replacement Cache (QM-ARC) policy. QM-ARC extends ARC by incorporating QoS-based priorities between data applications and customers using a penalty concept borrowed from service-level management practices. QM-ARC is generic, applicable to any number of cache tiers, and can accommodate various penalty functions. Furthermore, we introduce a complementary feature for QM-ARC that employs Q-learning to dynamically adjust the sizes of the two ARC lists. Our solution, evaluated using both synthetic and real-world traces, demonstrates significant improvements in QoS compared to state-of-the-art methods by better considering priority levels. Results show that QM-ARC reduces penalties by up to 45% and increases the hit rate for high priority data by up to 84%, without negatively impacting the overall hit rate, which also increases by up to 61%.

The rapid expansion of data volumes across various scientific and technical fields, along with the development of exascale computing in the high performance computing (HPC) domain, continually challenge existing storage systems. These systems typically consist of heterogeneous multi-tier storage architectures, ranging from high-speed solid-state drives (SSDs) tier with limited storage capacity to slower magnetic tapes tier with larger storage capacity. A significant challenge in HPC storage systems is the effective placement and migration of data across different storage levels. Current strategies, such as those implemented in parallel file systems like Lustre, utilize hierarchical storage management (HSM) solutions such as the Robinhood Policy Engine, which operate at the file granularity level for data eviction policies. In contrast, traditional caching policies work at the block level. This mismatch of granularity makes it difficult to adopt traditional eviction policies to those HSM. This study introduces a new multi-criteria file-level eviction policy incorporating frequency and recency of access, file lifetime, and a fairness criterion. Our policy reduces I/O processing times by average of 30% for tested workloads and improves the hit ratio by 56.43% on average, outperforming block-based cache replacement policies such as LRU, LFU, and ARC.

The emergence of multi-core architectures in space systems presents a real challenge in terms of predictability. Asymmetric multiprocessing (AMP) architectures attempt to solve this problem by approaching uniprocessor behavior. In this paper, a new real-time communication model for AMP architectures is presented. The paper demonstrates, by logic, the predictability of the model, and describes a set of evaluations designed to prove it.

Modern real-time embedded systems increasingly integrate software with varying criticality levels, which increases the interest in mixed criticality scheduling (MCS). MCS provides runtime adaptation mechanisms when low criticality tasks exceed their allocated execution budgets in order to guarantee the timing constraints of high criticality tasks. Most of the current research on MCS adaptation mechanisms focuses on guaranteeing timing constraints by interrupting and discarding low criticality tasks when their budgets are exceeded. They consider only the temporal dimension, without taking into account the quality of the results obtained. Quality is defined as the accuracy level of the results computed by a task within a given execution time. In this article, we propose an approach to integrate quality in a new task model to establish a relationship between quality and scheduling design. We propose the q-AMC scheduling algorithm to validate our task model. This algorithm integrates quality degradation into the scheduling adaptation mechanism. Simulation-based experiments show that our approach increases the quality up to 44.6% compared to the original AMC approach.

This paper presents an approach, called CosiCosi, whose the aim is to characterize the temporal behavior of complex systems. The analyzed systems are defined by their software and hardware architectures, and by the duration of the processing jobs. The abstraction of jobs by their execution time enables early verification, at a phase where all the implementation details of the components are not yet defined. The tool that supports the verification is a SystemC simulator configured from AADL architecture models. It simulates the temporal behavior of the model components, respecting the AADL runtime specification as defined in the standard. The targeted use of the tool is the qualification of hardware/software architectures through intensive testing under an expected workload. The evaluation shows the tool's ability to simulate a system composed of 600 threads, over 1 hour of operation, in approximately 2 minutes on a desktop computer.

Nowadays, many functionalities are integrated in embedded real-time systems, leading to an increase in the number of their software and hardware components. In this context, the interest in mixed-criticality scheduling is growing [1].

Distributed data-centric systems, such as Named Data Networking, utilize in-network caching to reduce application latency by buffering relevant data in high-speed memory. However, the significant increase in data traffic makes expanding memory capacity prohibitively expensive. To address this challenge, integrating technologies like non-volatile memory and high-speed solid-state drives with dynamic random-access memory can form a cost-effective multi-tier cache system. Additionally, most existing caching policies focus on categorizing data based on recency and frequency, overlooking the varying Quality-of-Service (QoS) requirements of applications and customers-a concept supported by Service Level Agreements in various service delivery models, particularly in Cloud computing. One of the most prominent algorithms in caching policy literature is the Adaptive Replacement Cache (ARC), that uses recency and frequency lists but does not account for QoS. In this paper, we propose a QoS-aware Multi-tier Adaptive Replacement Cache (QM-ARC) policy. QM-ARC extends ARC by incorporating QoS-based priorities between data applications and customers using a penalty concept borrowed from service-level management practices. QM-ARC is generic, applicable to any number of cache tiers, and can accommodate various penalty functions. Furthermore, we introduce a complementary feature for QM-ARC that employs Q-learning to dynamically adjust the sizes of the two ARC lists. Our solution, evaluated using both synthetic and real-world traces, demonstrates significant improvements in QoS compared to state-of-the-art methods by better considering priority levels. Results show that QM-ARC reduces penalties by up to 45% and increases the hit rate for high priority data by up to 84%, without negatively impacting the overall hit rate, which also increases by up to 61%.

The rapid growth of global data traffic has exposed limitations in traditional content delivery architectures. Information-Centric Networking (ICN) addresses these challenges by leveraging in-network caching to enhance scalability, reduce latency, and improve overall performance. However, existing caching strategies either optimize single-node cache management without considering network-wide costs, or address distribution without hardware-aware cost modeling. We propose a unified, cost-aware distributed caching strategy that integrates multi-tier caching at each node with network-wide replication, guided by a comprehensive cost model including resource depreciation, bandwidth, energy, and Service Level Agreement compliance. Our approach minimizes redundant replication on the network while maximizing cache hit rates and reducing latency. Experiments show on average 19.15 %, and up to 45.19 %, cost reduction, 8.11 %, and up to 32.15 %, cache hit ratio increase, and 9.01 %, and up to 27.21 %, latency improvement over other methods, offering a cost-effective solution for next-generation ICN systems.

Interference within a multi-core architecture may have several origins. Understanding where interference comes from is mandatory for verification and certification purposes. Unfortunately, the complexity of current architectures makes it difficult to quantify such interference. In this article, a new approach is introduced that enables benchmark configurations to isolate and quantify interference. An experiment with DMA interference is presented and shows a WCET overhead of up to 0.26% at 25 Mbit/s. This experiment was also able to discover and identify interference related to DMA, such as interruptive flow overhead, around 3% for 25 Mbit/s, or packet transmission memory access overhead, around 9% for 25 Mbit/s.

Random forests is a widely used classification algorithm. It consists of a set of decision trees each of which is a classifier built on the basis of a random subset of the training data-set. In an environment where the memory work-space is low in comparison to the data-set size, when training a decision tree, a large proportion of the execution time is related to I/O operations. These are caused by data blocks transfers between the storage device and the memory work-space (in both directions). Our analysis of random forests training algorithms showed that there are two major issues : (1) Block Under-utilization: data blocks are poorly used when loaded into memory and have to be reloaded multiple times, meaning that the algorithm exhibits a poor spatial locality; (2) Data Over-read: the data-set is supposed to be fully loaded in memory whereas a large proportion of data are not effectively useful when building a decision tree. Our proposed solution is structured to address these two issues. First, we propose to reorganize the data-set in such a way to enhance spatial locality and second, to remove the assumption that the data-set is entirely loaded into memory and access data only when effectively needed. Our experiments show that this method made it possible to reduce random forest building time by 51 to 95% in comparison to a state-of-the-art method.

In this article, we investigate the interest in applying a mixed-criticality approach to schedule convolutional neural network (CNN) applications on multicore architectures. We deal with software composed of real-time interactive applications and CNNs that have different criticality levels. A classical means to schedule software with various criticality levels is to apply partitioning methods to enforce spatial and temporal isolation, which may be inefficient if application execution times have a high level of variability. In that case, applying a mixed-criticality approach may improve resource usage. We conducted a measurement campaign to assess the variability of CNN execution time and investigate whether this kind of application could benefit from a mixed-criticality approach. The results show that the execution times of the chosen CNN application vary with an average execution time of 109 ms and a worst case of 252 ms. Furthermore, they indicate a potential save of computing resources up to 73 % when applying a mixed-criticality approach instead of partitioning methods.

Memory caching is a common practice to reduce application latencies by buffering relevant data in high speed memory. When the volume of data to cache is too large or a DRAM - based solution too expensive, several technologies such as NVM or high speed SSDs could complement DRAM to form a multi-tier cache. Additionally, most existing policies focus on categorizing the data based on factors like recency and frequency, setting aside the fact that applications/customers have varying Quality-of-Service requirements. This concept is well established in Cloud environment with Service Level Agreement (SLA). In this paper, by extending the Adaptive Replacement Cache (ARC), that uses recency and frequency lists, we propose a QoS-aware Multi-tier Adaptive Replacement Cache (QM-ARC) policy with the ability to take into account data applications/customers priorities through the concept of penalty borrowed from the Cloud. QM-ARC is generic, as it can be applied whatever the number of tiers and can accommodate different penalty functions. Using synthetic and real traces, our solution improved QoS as compared to state-of-the-art work.

In order to ease the early verification of uniprocessor real-time systems, the tool Cheddar provides a service that guarantees the applicability of a schedulability analysis method for a given architecture model. This verification service uses a catalog of design patterns. In this article, we propose to extend these patterns to multiprocessor architectures. Designing such extension is a challenge because the knowledge of both the software and the hardware architectures are essential to decide on the schedulability of a task set in that context. Indeed, parallel execution of tasks involves hardware resource sharing, that has in turn an effect on the task execution times. Currently, no general method is able to assess the schedulability of a high-performance multicore system with a limited level of pessimism, except if assumptions or usage restrictions are set to simplify the system analysis. So, the research community is developing multiple schedulability tests based on various assumptions which constrain the task models and their execution platforms. In this article, we propose a framework based on Prolog that allows engineers to verify the conditions to apply a test are met. Prolog facts model the software and hardware architecture, and the inference engine checks whether these facts conform to a design pattern associated to a given verification method. The design pattern compliance framework is integrated with the Cheddar tool. Three examples of multiprocessor analyses illustrate the proposal. A scalability analysis shows the tool is able to verify the compliance of architectures composed of 600 tasks and 60 cores, in less than 140 s on a desktop computer.