Spatial accelerator offers high performance for tensor computations, but it also brings significant challenges to map tensor computations on spatial accelerators. Automatic mapping is a promising direction for tensor mapping. However, existing methods either explore numerous invalid and inefficient configurations or rely on inaccurate evaluation of incomplete configurations, leading to suboptimal performance. Moreover, prior works typically formulate tensor mapping as a prime factor allocation (PFA) problem, which restricts tile factors to exact divisors of tensor dimensions, thereby excluding potentially beneficial non-divisible configurations. Irregular tensor tiling (ITT) relaxes this constraint by introducing remainder factors, but it incurs an enormous mapspace due to combinatorial explosion of tile-remainder pairs, leading to inefficient exploration. We propose Soter, an automatic tensor mapping framework that exploits ITT for efficient and flexible tensor mapping on spatial accelerators. First, Soter constructs a high-quality mapspace using an analytical model to eliminate invalid and inefficient configurations. Second, it employs a two-stage mapper that decouples the exploration of tile factors and remainder factors to improve exploration efficiency, and it leverages Transformer-based modeling and policy gradient optimization to avoid incomplete configuration evaluation. Finally, Soter coordinates the model and the mapper to jointly optimize both the mapspace and the tensor mapping configurations. The mapspace is identified by the model and is updated during the exploration of the mapper. Experiments show that Soter achieves up to 4.2× average speedup in latency and up to 9.1× average improvement in energy-delay product (EDP) over state-of-the-art mapping methods, while demonstrating strong scalability across larger tensor computations and spatial architectures.
Integrated circuits are critical components of cyber-physical systems, enabling advancements in smart sensing, computing, and more. However, the globalization of integrated circuit design and manufacturing has introduced security risks, such as hardware Trojans (HTs). Although deep learning approaches have demonstrated remarkable performance in HT detection, their effectiveness is typically predicated on the idealized assumption of complete netlist availability. In practice, obtaining a complete netlist is highly challenging due to limitations in the reverse engineering process, such as imaging resolution, inaccurate stitching, and interconnect extraction. Consequently, exploring HT detection methods for partial netlists has emerged as a critical research problem in hardware security. To address the above challenge, this paper proposes a novel HT detection framework for partial netlists, named RL-LASV. Guided by static signal probability (SP) as a local heuristic, the framework employs a reinforcement learning prediction model to reconstruct incomplete netlist structures. Subsequently, a LOG-SCOAP method is developed for HT detection. Extensive experiments are conducted on the Trust-Hub benchmarks to evaluate the framework across three levels of missingness. Experimental results show that the proposed method can effectively restore the netlist structure under different levels of missingness and improve HT detection performance.
As scientific research grows more complex, a wide range of HPC and AI ensemble workflows have been proposed, in which machine learning models learn from interactions with ensemble simulations. However, existing distributed frameworks and solutions fall short in facilitating this intensive interactions, struggling with challenges like non-trivial diverse task coupling, heterogeneous task management, and inefficient I/O and RPC operations. To address these challenges, we present RTAI, a distributed runtime system aiming at promoting the performance of emerging HPC-AI workflows on HPC clusters. Specifically, it consists of several essential components: RTAI Packer is a flexible abstraction that parallelizes and constructs a dynamic dependency graph of the workflow. RTAI Orchestrator improves the execution efficiency of task graph and cluster-wide resource utilization by adaptively organizing resources and scheduling diverse tasks, e.g. parallel computing tasks and RPC-based data processing and model training/inferring tasks. RTAI FileHub is a tailored ad-hoc file system that employs distributed in-memory caching for dynamically generated files to enhance I/O efficiency. To enhance the performance of RPC tasks and remote object accessing, we further design FastRPC, a high-performance RDMA-based RPC module, which can reduce task coupling latency and improve task throughput by customizing transmission strategies for varying message sizes and handling message queue at the RDMA layer. Experiments demonstrate that RTAI significantly outperforms HPC and AI workflow frameworks, reducing workflow makespan by up to 1.6× and achieving 5× higher I/O throughput.
Spiking Neural Networks (SNNs), the third generation of neural networks, are event-driven, brain-inspired models offering high energy efficiency. Recently, the emergence of Spiking Self-Attention (SSA) has further significantly improved the performance of SNNs. However, existing neuromorphic processors lack native support for SSA, resorting to resource-intensive simulations, general-purpose computation, or external offloading, thus failing to leverage full hardware potential. To address this limitation, we propose Dynamic Synapse (DySyn), a novel neuromorphic architecture that natively and efficiently supports SSA. DySyn is based on the principle that the multiplier in SSA is a sparse binary matrix, enabling neurons in the multiplier to dynamically control the spike routing from the multiplicand to the product matrix. To optimize resource consumption, we introduce a novel partitioning method that maximizes synapse reuse within a core. Furthermore, we design a spike coalescing mechanism tailored for DySyn to significantly reduce spike traffic and communication overhead. We evaluated DySyn on 10 SNN transformer workloads, including computer vision and natural language processing tasks. Experimental results demonstrate that DySyn outperforms previous neuromorphic processors, achieving an average speedup of 7.23x and a 183.57x improvement in energy efficiency.
