As the field of quantum computing moves towards the realization of Quantum Error Correction (QEC), an increasing amount of attention has been paid to the implementation of decoders-classical systems analyzing the state of error on the quantum device in real-time. However, today there is a lack of tools available to characterize and compare the performance of decoders. In this work, we address this need and introduce decoder-bench, a framework for benchmarking decoders on relevant QEC code traces. decoder-bench integrates with Stim, a high performance tool for analyzing stabilizer circuits, to create traces for a variety of QEC codes and fault-tolerant subroutines. We use decoder-bench to evaluate the accuracy and latency performance of multiple decoders for circuit-level simulations of color code memory experiments, bivariate-bicycle code memory experiments, surface code memory experiments, and surface code lattice surgery experiments.
The increasing complexity and performance requirements of extended reality (XR) platforms necessitate a full-stack approach to optimize system architectures. We present XRSight, a hardware-software co-design framework for developing and characterizing extended reality (XR) workloads on embedded systems-on-chip (SoCs). This open-source tool integrates a cycle-accurate, FPGA-accelerated simulation environment with a representative XR application suite to enable architectural exploration and detailed performance analysis. By bridging real-world XR workloads with a modular system-on-chip (SoC) platform, our framework offers fine-grained visibility into SoC execution behavior across compute, memory, and interconnect subsystems. We demonstrate the utility of our work through case studies that examine how different hardware configurations and workload mappings affect end-to-end system performance. Our results show how the tool can inform hardware design decisions and workload optimizations. This framework lowers the barrier to entry for researchers and architects exploring XR-centric system designs in an open and extensible SoC ecosystem.
Cheaper and more accurate sequencing technologies have led to a large volume of genetic data that poses significant computational challenges and requires novel computing solutions to keep pace. This increased volume has also enabled the use of pangenome graph references, which provide better quality alignments because they represent variation, but they require new algorithms that are usually slower than those using a traditional reference genome, and exhibit different computational characteristics.We introduce PangenomicsBench, the first benchmark suite targeting computational pangenomics, with six CPU and two GPU kernels extracted from popular tools, designed to guide future research in pangenomics software and hardware acceleration. We characterize these workloads to reveal the following key insights: (a) Seq2Graph mapping algorithms are limited by control complexity rather than memory access to the reference graph because they process small, cache-friendly subgraphs. (b) GPUs have the potential for large speedups, but are limited by control divergence for mapping workloads. (c) Pangenomics introduces computational patterns different from traditional genomics like stochastic gradient descent. (d) Pangenomic mapping algorithms are highly sensitive to reference graph structures. (e) There are opportunities for optimizing existing software.
Serverless computing has emerged as a competitive cloud computing paradigm. At the same time, the open-source RISC-V ISA has gained a lot of interest and the first RISC-V systems have already started to appear in the server market for datacenters. The combination of these computing trends necessitates the performance assessment of the impact of the RISC-V ISA and relevant processor implementations when executing serverless workloads. However, currently there is no benchmarking support for systematically evaluating serverless workloads on RISC-V systems. In this paper we bridge this gap in benchmarking support across the layers of the computing stack, from the application to the microarchitecture. We port the vSwarm serverless benchmark suite to the RISC-V ISA and enable the execution of the workloads in both real and simulated RISC-V platforms using the gem5 microarchitectural simulator. To demonstrate the usefulness of the infrastructure, we quantify the performance trade-off of cold vs. warm execution on a simulated RISC-V system and validate the results against a real platform. Overall, our enhanced benchmarking support creates new opportunities for further experimentation with serverless workloads on RISC-V systems, enabling the analysis and optimization of their performance across the computing stack.
