Cholesky factorization is a core operation in scientific computing, yet its scalability is often constrained by memory limitations when processing extremely large dense matrices. This work introduces an out-of-core Cholesky factorization algorithm for symmetric positive-definite matrices that integrates GPU acceleration, block-wise lossless compression, and parallel I/O to overcome these limitations. The approach leverages the OMPC runtime for asynchronous task scheduling and employs HDF5 to store the matrix on disk, taking advantage of Lustre's parallel I/O capabilities in distributed environments. Tiles are decompressed just-in-time on the GPU, significantly reducing host memory usage, storage footprint, and end-to-end data movement overhead-from disk through the CPU to the GPU-without compromising numerical accuracy. Experimental results show that the proposed method scales across 8 GPU nodes, successfully factorizing matrices up to 3M x 3M. In comparison, SLATE could only handle sizes up to 700K x 700K, with the proposed algorithm achieving up to 41% higher throughput. These results demonstrate the algorithm's scalability and competitiveness beyond memory-constrained in-core solutions, offering a practical path for enabling extreme-scale scientific applications.
The rapid scaling of deep learning (DL) models raises the need for accurate and understandable performance/energy prediction tools to support efficient resource management and sustainable AI development. Existing modeling approaches often lack both sufficient granularity to capture nuanced hardware-software interactions and suitable flexibility to adapt to diverse modern architectures. This paper introduces an analytical framework for time/energy prediction of DL training workloads on GPU. Our framework integrates detailed workload characterization that includes FLOPs, memory access, kernel activities, and novel structural features to derive an architecture-aware efficiency model, which considers a saturation-based function to capture dimensional scaling effects on hardware utilization. We propose an iterative refinement methodology, which incorporates model-specific scalars to address particular architectures like ALBERT and precision-specific calibrations for BF16 operations. Our benchmark with six advanced DL models (including CNNs, BERT-style Transformers, and LLMs like TinyLlama) on NVIDIA A100 GPUs under various configurations (1/4 GPUs, FP32/TF32/mixed BF16) shows that our approach achieves a high predictive accuracy, with an overall relative error of 4.14% (3.05% for time, 5.78% for power). The framework is intended to provide valuable insights for HPC-AI co-design, energy-aware scheduling, and performance optimization.
Training in supervised machine learning is based on the availability of datasets; however, medical datasets must comply with stringent privacy regulations. Generative Adversarial Networks (GANs) are a relevant alternative to solve the limitation of small medical datasets due to their ability to generate additional data with desired features. A significant drawback of these models is that they may produce unrealistic, blurred, or insufficiently diverse images. This paper proposes a data augmentation technique using GANs to create synthetic Magnetic Resonance Imaging (MRI) of four stages of Alzheimer's Disease (AD): non-demented, very mild demented, mild demented, and moderate demented. We designed a GAN based on the Pix2Pix model, which learns the features of each AD stage. Generated images are evaluated by multistage Convolutional Neural Network (CNN) models, greyscale histograms of the distribution of pixel intensities, and brain mass measurements on binarized images. The results indicate that AD synthetic MRI effectively captures disease patterns, demonstrating the potential of GANs to improve training and diagnosis of neurodegenerative diseases.
Recently, Graph Neural Networks (GNN) have been integrated into various local applications, such as local community detection and local code assistant, making edge inference increasingly important. To support diverse workloads, state-of-the-art edge devices have evolved into heterogeneous platforms, integrating components like CPU, GPU, and NPU. To this end, we propose GNX, a novel GNN system that accelerates GNN inference on edge heterogeneous platforms by leveraging all the heterogeneous processing units. Given a GNN model and a heterogeneous platform, GNX automatically generates parallel execution plans, consisting of both data and pipeline parallelism. To reduce the complexity of the design space, GNX converts GNN models into coarse-grained blocks and performs the search at the block level. By leveraging the APIs provided by state-of-the-art heterogeneous frameworks, GNX can flexibly schedule various parallel execution plans and seamlessly adjust the workload across the heterogeneous processing units for load-balanced execution. Our study shows that GNX effectively accelerates three widely-used GNN models on two state-of-the-art edge heterogeneous platforms. Compared with the baseline approach that uses only a single processing unit, GNX achieves up to a 2.57x speedup. Compared with adopting data parallelism and a state-of-the-art scheduler, GNX achieves up to 1.90x and 1.79x speedup, respectively. We also discuss the applicability of and extensions to GNX to support other GNN models.
As GPU architectures continue to diversify across high-performance computing (HPC) systems, ensuring code portability and minimizing environmental impact have become critical challenges. This paper investigates how different programming models affect the carbon-performance efficiency of a Reverse Time Migration (RTM) application, a key workload in geophysics. We provide twelve implementations of the RTM code using CUDA, HIP, Kokkos, RAJA, and OpenMP Target, and evaluate their behavior on eleven GPUs from NVIDIA and AMD. Our analysis covers execution time, energy consumption, and carbon footprint. Results show that HIP, when tuned per architectures and RAJA, achieve the highest code portability in terms of carbon-efficiency, reaching up to 93.7% and 93.4% efficiency across all platforms, respectively. Overall, while HIP and CUDA deliver peak performance and the lowest emissions when properly optimized, the gap between these native models and high-level abstractions such as RAJA and Kokkos is steadily narrowing, indicating growing potential for portable and sustainable HPC development.
