The materials and processes for fabricating a compact multiple-element slab waveguide spectrograph suitable for multimode fiber-optic wavelength-division-multiplexing (WDM) applications are described. A fabrication scheme based on thick-film solder glass glazing, hot-press lamination and optical finishing was chosen to produce a precisely dimensioned glass-ceramic spectrograph blank structure that is compatible with grating replication manufacturing technology and suitable for hermetic packaging. The laminated blank consists of alternating layers of glass-ceramic spacer plates and optical glass wafers bonded together with a screen-printed solder glass adhesive. The exact interlayer optomechanical registration, achieved in the laminated spectrograph blank was essential for obtaining spectral referencing functionality and a passive alignment packaging scheme. A spectrograph optical subassembly package was developed and implemented as part of a multichannel spectrum analyzer receiver in a prototype optical WDM sensor interface system.< >
This paper describes a series of studies to evaluate the long term surface mount attachment reliability of TSOPs using thermal cycling as an acceleration method. Visual inspections, pull strength, and scanning electron microscopy were used to characterize the solder joints. In addition, the solder plating, lead wetting and aging characteristics were evaluated. Failure during thermal cycling was primarily caused by the coefficient of thermal expansion (CTE) mismatch between the package and the printed wiring board. Using acceleration factors based on solder joint strain energies induced by global and local mismatches during thermal cycling, the experimental results are extrapolated to various use conditions and life expectancies. The TSOP solder joint reliability depends on environmental conditions (cyclic temperature range, temperature maximum and dwell time), board thickness and materials, product intended service life and expected hazard rate limits.<>
A first-level-metal single-conductor IC interconnect model is developed for high-speed and high-density VLSI circuit design. The model shows interconnect circuit parameters that vary with frequency. Existing interconnect models exclude effects such as capacitive fringing and the influence of substrate conductance. The new model represents fine-line as well as wide-line interconnect behavior over a 20-GHz frequency range and includes these effects. The model parameters are compared to scattering parameter measurements as well as numerical simulations based on PISCES-II. Excellent agreement is shown with S-parameter measurements
Electrical contact failure due to thermal decomposition of low-molecular-weight silicone vapor evaporated from such silicone products as oils and rubbers was investigated in a simulated environment. A glassy film deposit was found on the contact surface after exposure to elevated temperature in an atmosphere containing an extremely small quantity of the silicone. The film was clearly identified as amorphous SiO/sub 2/ by ellipsometry, X-ray photoelectron spectrometry (XPS), and X-ray diffractometry (XRD). The growth of the film was directly related to the concentration of silicone vapor and temperature. The growth law was an exponential function of the exposure time. The film increases static contact resistance when it is thicker than 800 AA and the load is less than 5 g. The relationship between the concentration of the vapor, temperature, film thickness, and contact resistance is represented schematically. >
The rapid emergence of multichip modules (MCMs) and the continuing interest in wafer scale integration (WSI) provide important opportunities for successful insertion of high performance optical interconnections into real systems. The large area substrates and the distances between packaged wafer-level modules introduce distances of sufficient length that propagation of very high-speed digital signals along electrical lines will be difficult. At the same time, the substrates allow use of thin film technologies for fabrication of optoelectronic devices, optical waveguides, and other optical elements, drawing on the natural alignment accuracy of photolithographic definition of optical components to avoid several practical problems arising when optical elements are surface mounted. For such reasons, large area silicon wafers provide an important potential application for more aggressive use of optical interconnections. An important issue is growth of GaAs semiconductor regions within a silicon WSI or MCM substrate containing high performance silicon CMOS circuitry, seeking to co-integrate optical and silicon VLSI devices. Experimental studies of submicrometer CMOS device characteristics following thermal simulation of GaAs heteroepitaxial growth are summarized
Generally, the package crack mechanism in the solder reflow process has been considered as follows: The plastic absorbs moisture during storage and the absorbed moisture is vaporized at the interface between the die pad and the plastic by heat in soldering. The vapor pressure generates delamination, deformation, and stress in the plastic. Thus the crack occurs if the stress exceeds the flexural strength of the plastic.However, a new mode crack that cannot be explained by a conventional cracking mechanism has been observed under the current circumstance of the surface mount components being smaller and thinner and requiring more severe characteristics in the solder reflow process. This new mode crack is generated from the upper portion of the die pad corner, not caused by the delamination between the die pad and the plastic.The new mode crack mechanism can be explained in this way: Absorbed moisture reaches the die attachment layer during storage and is vaporized by heat in the soldering; the vapor pressure pushes down the die pad and causes stress in the plastic of upper portion of the die pad corner; then new mode cracks occur. A new lead frame design that can prevent this crack is described.
A Monte Carlo analysis of aged crossed rod copper contacts is conducted to evaluate the effects from a number of variables such as film thickness, contact force, microhardness and geometry. The analysis is conducted using two models that employ material properties and design parameters as constraints in a statistical model of degradation. It is shown, using a power law model to describe the surface concentration of oxides, that the degradation model can be calibrated to produce results that show good agreement with a wide range of laboratory data. It is found that the observed difference in performance of soft and hard copper contacts can be explained within the framework of the degradation model. It is concluded that the mechanism which causes oxide accumulation in the surface layer is affected by microhardness in a way which is less favorable to the performance of soft copper contacts.<>
A fine pitch chip-on-glass (COG) bonding technique for liquid crystal display (LCD) panels has been developed. An IC chip with gold bumps was dipped in a stirred indium alloy bath in a nitrogen atmosphere without flux. Shallow-bowl-shaped In alloy bumps were selectively formed on the Au bumps on the IC electrodes. The minimum bump pitch was 50 /spl mu/m, and the bump size was 31 by 31 /spl mu/m. The In alloy bumps whose minimum pitch was 100 /spl mu/m were connected to molybdenum conductors without flux at low pressure (30 gf/bump or less) and low temperature (110/spl deg/C or less). The temperature was lower than the alloy melting point. The mean contact resistance was 0.78 /spl Omega/. It was found that the calculation of the minimum bump pitch for the bump sizes and the In alloy bump height is useful for designing new ICs with fine pitch bumps. It has been demonstrated through a thermal shock test (TST), a high temperature and high-humidity storage test; and a high-temperature storage test that the contact resistance changes satisfied the specification. Prototype TFT-LCD panels with 80-/spl mu/m pitch driver ICs were successfully developed.<>
Recent developments in computer-aided design have made possible the highly automated layout of custom ECL (emitter coupled logic) circuits. These layouts have a much higher circuit and power density than gate array designs. It is now possible to place an entire ECL microprocessor, including floating point unit and cache memory, on one large die. To demonstrate the capability of supporting such a die, the authors built and tested low-cost, air-cooled single-chip packaging for a 12.6-mm*15.4-mm die. The PPGA (plastic pin grid array) package supplied the required current and maintained junction temperatures at less than 100 degrees C while dissipating 150 W. This required innovation in five areas: die metalization, bondwire layout, PPGA package design, die attach, and cooling by a thermosiphon.<>
A high pin count, high performance PGA has been developed for next-generation ASIC devices which apply half-micron BiCMOS technology and have a maximum usable gate count of 300 K. In view of the advances in CMOS and BiCMOS ULSI technologies, high performance packages are required. This new package has been designed with due consideration of all package functions. Packages for high-end devices need to satisfy the following requirements: high electrical performance, low thermal resistance and high pin count in keeping with easy routing of PWB. The body size of the developed package is 60/spl times/60 mm/sup 2/. Surface mount type pin joint was adopted to realize high wiring density of a printed wiring board. This package has 820 pins with 50 mil pitch, and 5 rows. A small pin diameter of 0.2 mm and a short pin length of 3.0 mm were used for surface mounting.<>
Any detailed discussion of high performance packaging for the next generation electronics systems must include both hybrid wafer scale integration (H-WSI) and monolithic wafer scale integration (M-WSI). A H-WSI circuit is a multichip module (MCM) that contains 20-50 chips with at least ten times the maximum functionality that can be readily achieved in one complex chip. A M-WSI circuit is a monolithic semiconductor (silicon generally) chip that contains a large number of cells that in total contain at least ten times the functionality that can be readily achieved in one complex chip. These devices could be called a system on a chip. This paper describes the driving forces behind WSI technologies, defines where the H-WSI technologies are today and forecasts where these are likely to evolve to in the future.< >
This paper investigates the use of a non-reactive plasma formed in a radio frequency discharge as a treatment to various substrates to reduce or eliminate the organic and inorganic contamination which prevents intimate interfacial contact. Argon was investigated as the plasma gas. The effect of time, chamber pressure, and power were studied. A goniometer was utilized to measure wetting contact angles as a quantitative measure of the cleaning effectiveness of the surface treatment. ESCA (electron spectroscopy for chemical analysis) data are correlated to substrate hydrophilicity, delamination and package cracking. The results show the argon plasma treatment to be an effective mean of reducing interfacial organic and inorganic contamination and improving the polyimide to mold compound adhesion. The improvement in package cracking performance brought about the argon plasma treatment is significant.<>
This paper presents a high-speed multifunction chip for performing one of four nonlinear operations: 1) square root, 2) reciprocal, 3) sine/cosine, and 4) arctangent. Each of these functions is evaluated with one ROM access, two additions, and one major and one minor multiplication, yielding a new result every two clock cycles. Its performance signifies an estimated three-to-four-fold increase in speed (for comparable technologies and minimum feature size) over existing approaches. Furthermore, since all four functions are performed on the same cell, a silicon-area advantage of approximately three is realized when the application demands multiple functions. In wafer scale integration (WSI) of signal and image processing algorithms, several such functions are usually needed, while defect tolerance dictates the use of just one or two types of cells. Thus the new component is ideally suited for monolithic WSI. However, it can also be used as a co-processor/accelerator for commercial DSP chips in hybrid WSI implementation of signal processing algorithms. The underlying principle, which has made the combined goals of high-speed and multifunctionality possible, is second-order interpolation of very small ROM tables. Two versions am presented: a 24-b chip, and a 16-b chip, both fabricated in 2.0-mum CMOS technology. As an application example, a rapid prototyping wafer scale architecture is described.
The electrical design, analysis and performance of tabular capacitors are presented. Simple formulas for capacitances are derived for spiral and concentric type tabular capacitors. By numerical methods the regions of greatest electric stress in the dielectric are found. The influence of bumps on the capacitor plates is examined by the method of conformal transformation. It is shown that a small circular ridge running the length of the capacitor can reduce the voltage rating by 50%. The inductance of the capacitor sets an upper bound on the highest frequency at which the capacitor behaves ideally. It was previously shown that high frequency behavior is influenced by the particular connection used in a capacitor. For a spiral wound tabular capacitor one type of connection is considered, and its equivalent circuit is exhibited. For concentric cylindrical tubular capacitors the only type of connection possible is the one considered for the spiral-wound capacitors. For that configuration a closed form electrostatic induction coefficient and inductance coefficient matrices are presented and used for high frequency analyses
Some characteristics of the transmission behavior of interconnections on conductive silicon substrates are presented. With regard to the signal propagation on high-speed digital circuits the broadband behavior of the lines is of special interest. The characteristic impedance and the propagation constant of the lines are determined experimentally by microwave measurements. The influence of the line geometry, the substrate resistivity and the signal frequency on the transmission behavior are clarified. Based on the results of the measurements, the suitability of the conventional RLC line model for time-domain simulations of the transmission characteristics of interconnections on silicon substrates is investigated.
Room-temperature capacitance-voltage-frequency measurements are reported for an 85-nF barium titanate high-voltage ceramic-disk nonlinear capacitor, intended for use in a power electronics turnoff snubber circuit. Bias-voltage excursions are from 0 to 1500 V DC, and the frequency responses are measured from quasi-DC to 1000 Hz. The observed C-V-frequency responses are modeled in terms of series-capacitance contributions from ferroelectric grains and p-n junction grain boundaries, involving 16 parameter variables. The ferroelectric capacitance terms are given by a modified Langevin function, and the grain-boundary capacitances are modeled by back-to-back p-n junction diodes on either side on an insulator boundary. The observed frequency dependence of the C-V response is attributed here to a Debye-type relaxation of the compensation regions at the grain boundaries, with time constant 15 ms. Good agreement between theory and experiment is obtained over the 0-1500-V bias range
Conductive particle-filled adhesives have been widely used for flex-to-rigid board interconnections in many consumer electronics, such as calculators and palmcorders. Most of the applications were in coarse pitch interconnections where the adjacent conductor's distance is greater than 0.4 mm. The success of coarse pitch applications has increased the interest to use such adhesives in fine pitch applications, such as flip-chip on board interconnection. Since these materials contain metallic particles to conduct currents in the z-direction (i.e., perpendicular to the plane of circuit board), their propensity for metal migration is a concern. Therefore we have applied accelerated temperature, humidity and bias (THB) tests to a group of materials designed for fine pitch applications. The accelerated life test conditions were 85-degrees-C/85%RH at three different voltages: 10 V, 50 V, and 100 V. The studies were focused on the samples' time-to-failure as well as the associated conduction and failure mechanisms. The test results showed significant metal migrations, and we are proposing enhanced electric field streSseS (10(2) to 10(4) V/MM) as the driving force for failures.
Conductive adhesives have been used in the electronics industry for several years to attach chips to package lead frames in the semiconductor industry and for general interconnection of components to flexible circuits for various consumer products. Generally, these materials conduct equally in all directions. To obtain pad isolation, the adhesives are screen printed to the pattern of the circuit pads. In the last few years, a new class of adhesives that are conductive in a single direction have been developed. These are referred to as Anisotropic Conductive Adhesive Films (ACAF). These anisotropically conductive adhesives provide electrical as well as mechanical interconnections for fine pitch applications. The conductivity of ACAF materials is only in the Z-direction (perpendicular to the plane of the board) while electrical isolation is maintained in the X-Y plane. Currently, at least 15 ACAF materials are commercially available. We have developed a methodology for evaluating these materials for their mechanical and electrical properties and interconnection use in the 8 to 15 mil pitch range. In addition, we characterized the materials as to their physical properties and cure characteristics. This paper details our findings with a comparison of physical form to assembly/cure and final electrical properties. We include in this study data from scanning electron microscopy, thermal analysis of the ACAFs, and cure and assembly studies on mixed substrate test vehicles. Information on initial electrical testing and long term reliability testing is also given.< >
The goal of the research reported here is to develop a general approach and the necessary methodologies and tools to allow circuit card assembly manufacturers to determine the optimal strategy for operating an assembly line, and to rapidly generate optimal or near-optimal line setups. The objective is to maximize total production rate over a desired product mix subject to capacity, technological, and production requirement constraints for the planning horizon. The authors develop the decision problems required for process planning, discuss their approaches to solving the decision problems, and present some case study results
The accuracy of the three predominant techniques for measuring the surface temperatures of GaAs ICs under operation was investigated. The most important result is that the precision of commercially available computerized infrared microscopy is more limited than previously believed, especially in the case when the minimum IC element size is smaller than its spatial resolution. Some type of emissivity correction is necessary to obtain high precision. At this stage, therefore, the diode drop technique, an electrical method, and the transition point technique, a liquid crystal method, or their combination, must be used for measurement with high accuracy. The transition point technique has been determined to have a precision as great as +or-2 degrees C for measurement at the actual hot spot of non-sealed GaAs ICs. The diode drop technique is the only method which is useful for sealed ICs.<>
