This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500°C silicon carbide (SiC) electronics and sensors, and test results of packaged SiC JFETs and capacitive pressure sensors at 500°C.

Immersion, single phase free convection cooling of multichip modules on a printed circuit board in a pool of dielectric fluid was examined numerically, with experimental verification of baseline cases. A multi-chip module with multiple thermal test cells with temperature sensing capability was simulated. The commercially available computational fluid dynamics program from ANSYS, Fluent, was used with the electronics packaging front end, Icepak, employed to create the models and compact conduction modules. Simulations were first performed of an experimental test vehicle which had five 18 mm by 18 mm die, arranged in a cross pattern, equally spaced die, 25 mm between them. Two of the die were aligned vertically with the center die, two aligned horizontally with it. The board was suspended vertically in a large pool of dielectric fluid. Heat was dissipated in the die at a flux of up to 2 W/cm2, based on the die surface area. Simulation results were compared with experimentally measured die temperature values and excellent agreement was seen for the cases of one die heated and all five die uniformly heated with the board cooled by FC-72. A numerical parametric study was performed to examine the effect of die size and spacing on temperature rise. In addition to FC-72, immersion cooling in Novec 649 and HFE 7100 were modeled. Design guidelines are suggested for dielectric fluid immersion cooled multichip modules.

We have described the modeling, circuit design, system integration, and measurement of a Remote Sensor Interface (Figure 20) that took place over a span of 5 years and 8 fabrication cycles. It was conceived as part of the Multi-Chip Module (MCM) shown in Figure 21, which also includes a digital control chip for clocking, programming, and read-out. Further work beyond the scope of this was performed to validate the RSI for the extreme environmental conditions of a lunar mission, and individual blocks are presently.

A hermetic multichip power package for silicon carbide devices that will operate at 200 degrees C ambient and switch 50-100 A has been developed. The Al2O3/MoCu structure, in which the SiC junction field-effect transistors and diodes are attached, was designed to hermetically seal the device areas. Details of the materials and processes used to fabricate the package are discussed. Die attach, ribbon bonding, and lid attach, as well as thermal modeling, electrical testing, and thermal cycling results are also described.

A multilayer dielectric and an encapsulation glass for Si 3 N 4 substrates has been successfully developed. Both multilayer dielectric and encapsulation glass showed good wettability, no cracking, and no bubbling. They showed good adhesion to the Si 3 N 4 substrates as evidenced by high pull strengths of 7.2-8.3 ksi for the multilayer dielectric and 7.6-10.8 ksi for the encapsulation glass. The leakage currents were measured with a Keithley 6517A Electrometer/High resistance meter at temperatures of -180°C to 125°C. As expected the leakage current decreased with decreasing temperature. At all the measurement temperatures, the leakage currents were less than 0.1 nA (10 -10 A). Test vehicles (TV) were designed and fabricated to characterize the robustness of the substrate metallization and dielectric, the die attach material and process, and wire bonds as a function of aging and thermal cycling. The Au conductor has strong adhesion on Si 3 N 4 before and after storage tests. While the dielectric has strong adhesion to the thick film Au, the adhesion of the dielectric to Si 3 N 4 was 60 lbs, but does not significantly change upon storage at -180°C or +125°C. Semiconductor die attach with indium performs and Au thermosonic wire bonding was also studied. The die shear strength was measured initially and after aging at 125°C. High temperature aging was selected for the test as intermetallics grow more rapidly at elevated temperatures. The die shear strength actually increased with aging. Wire bond pull strength, ball shear and electrical resistance were also measured initially and after aging at 125°C. The ball shear strength and resistance remained stable with aging, while the wire pull strength decreased slightly due to annealing of the Au wire. A SiGe Butterworth filter was designed, fabricated, and tested using the thick film Si 3 N 4 substrate technology assembled in a 14-pin DIP-style multilayer package. The successful operation of this circuit demonstrated both device and package functionalities over the temperature range of -180°C to +125°C.

With the increasing electronics demand on complexity and functionality, low temperature cofired ceramic (LTCC) shows its advantages for cost efficiency under high volume, multilayer high packaging density, and compatibility of passive components integration. However, compared with thin film technology, the minimum thick film line width and spacing on LTCC is 4mil, which limits the packaging of fine pitch devices. In this study, one of DuPont™ photoimageable thick film gold (Au) conductors has been selected to fabricate on DuPont 951PX substrate, with the patterns as small as 1mil. Surface insulation resistance (SIR) and serpentine resistance patterns with a series of line width and spacing was printed and post fired on LTCC to investigate the capabilities and limits of the feature size. Feature dimensions were measured to compare with the design value. Metal adhesion and stud bump patterns are also included in the test substrate. After initial testing, the substrates are undergoing 300°C aging. Post aging resistance measurement, metallization adhesion pull test and Au stud bump shear test are carried out to evaluate its high temperature behaviors.

A thin film material and process technology is being developed and evaluated for high temperature (300°C) digital multichip modules for use in geothermal well instrumentation. The substrate technology selected is AlN to minimize the difference in the coefficient of thermal expansion between the substrate and the SiC digital die. A thin film/plated Ti/Ti:W/Au metallization is used with a plasma enhanced chemical vapor deposited Si3N4 to create multilayer interconnections. Active components are assembled to the interconnect substrate using Au stud bump thermocompression bonding. The Au stud bump maintains a monometallic interface between the substrate Au pad surface and the Au pads on the SiC die. A digital circuit has been built and successfully tested as an initial demonstration.

An all SiC 600V / 6 m hermetic half-bridge power module has been developed to operate at ambient temperatures of 200oC and with junction temperatures near 250oC. The modules use SiC trench JFET technology and can output over 100A at Tj=250oC. Double pulsed switching was performed up to temperatures of 150oC with a measured total switching energy of 0.73mJ

Geothermal well logging and instrumentation applications require high-temperature logging tools and sensors with long-term operation capability at 300 degrees C. Advanced SiC technology has enabled high-temperature electronics. To build functional systems operating at high temperatures, an interconnection and packaging technology must be developed to interconnect SiC devices and passive components. Off-eutectic AuSn has been evaluated for SiC and passive component attachment to PtPdAu/Au thick film metallization on alumina substrates and on thick film dielectric. A functional SiC-based oscillator module was fabricated and tested to demonstrate the assembly technologies developed for 300 degrees C applications.

For electronics operating at 300°C, thick film technology has been proposed as a suitable interconnection technology to create modules. This work examines the leakage current with constant bias (100V) at 300°C. The leakage current increased significantly within the first few hours of aging. The effect of 300°C aging with dc bias on the adhesion of multilayer thick film test structures was also studied. The aged adhesion was a function of bias polarity. Fracture surface analysis results are presented. Bi in the PtPdAu conductor appears to play a role in both the leakage current and adhesion phenomena observed.

Digital silicon carbide integrated circuits provide enhanced functionality for electronics in geothermal, aircraft and other high temperature applications. A multilayer thin film substrate technology has been developed to interconnect multiple SiC devices along with passive components. The conductor is vacuum deposited Ti/Ti:W/Au followed by an electroplated Au. A PECVD silicon nitride is used for the interlayer dielectric. Adhesion testing of the conductor and the dielectric was performed as deposited and after aging at 320°C. The electrical characteristics of the dielectric as a function of temperature were measured. Thermocompression flip chip bonding of Au stud bumped SiC die was used for electrical connection of the digital die to the thin film substrate metallization. Since polymer underfills are not compatible with 300°C operation, AlN was used as the base ceramic substrate to minimize the coefficient of thermal expansion mismatch between the SiC die and the substrate. Initial die shear results are presented.

Silicon nitride (Si3N4) offer potential advantages as a substrate for high temperature power packaging. Si3N4 has higher fracture strength than alumina and aluminum nitride. The coefficient of thermal expansion (CTE) of Si3N4 is ~3 ppm/°C and the thermal conductivity ranges from 30–50W/m-K. Active metal brazed Cu-Si3N4 substrates are commercially available for power modules. However, the large mismatch in CTE between Si3N4 and Cu results in ceramic fracture and delamination with the wide temperature thermal cycling ranges encountered in high temperature applications. In this work Cu-Carbon and Cu-Mo metal matrix composites have been investigated to reduce the CTE mismatch. The process details are presented along with finite element modeling of the proposed structure. Ultimately, the proposed structure was unsuccessful.

Highly accelerated life testing (HALT) is used to quickly assess the reliability of passive components for geothermal applications operating at 300°C ambient temperatures. The HALT methodology uses combined stresses to accelerate the failure of capacitors and resistors. This paper describes the test methodology and results on capacitors and resistors at 300°C and 350°C. Life models for the components are presented.

The challenges of packaging SiC-based electronics for high-temperature applications include their high operating temperatures, wide thermal cycle ranges, and, sometimes, high currents and high voltages. As a result, the selection of metallurgy for high-temperature SiC die attach is crucial to a successful package design, which involves chip metallization, substrate metallization, and die attach alloy. This paper examines off-eutectic Au-Sn as the die attach alloy with a PtAu thick film metallization on AlN substrates. A pure Au thick film layer was printed over the PtAu thick film layer. AlN substrates metalized with refractory MoMn and electroplated Ni/Au were also used. Two different die attach approaches have been investigated, using Sn-Au-Sn off-eutectic thick foil and limited-volume eutectic AuSn (80/20 wt.%) preform. The SiC backside metallizations evaluated were Ti/TaSi 2 /Pt/Au and Cr/NiCr/Au. Die shear tests were performed after aging at 500°C and after thermal cycling. The shear test results and failure surface analysis are discussed.

In this paper, a heat spreader attachment with indium solder for high-power flip chip-in-package application was investigated. The Cu heat spreader was metallized with Ni/Au and the flip chip die backside metallization was Ti/Au. A low voiding attachment process was achieved with vacuum soldering. The Au thin film was converted into AuIn 2 completely after initial soldering, but no intermetallic compund (IMC) formation between Ti and In was observed. The attachment had good mechanical strength as measured by shear testing. The shear strength was not degraded significantly after multiple lead free solder reflows or with thermal aging at 120°C. For thermal shock cycle test (-40°C to 85°C), die with Ti/Au (2000 A¿ of Au) metallization had early partial delamination. The effect of Au thickness on mechanical strength was further evaluated. Assemblies (Cu on Si) with Ti/Au (2000 A¿) die had lower shear strength compared with Ti/Au (3000 A¿) and Ti/Au (4000 A¿ ) die. The pull strength (Si on Si) increased with increasing gold thickness. Thermal shock testing (-40°C to 85°C) for assemblies with Ti/Au 3000 A¿ along with Ti/Ni/Au (control) did not show early delamination and had similar performance after 2000 cycles.

This talk will review the soldering process, with flux and without flux, followed by solid-state bonding and flip-chip interconnects using pure silver (Ag) columns or joints. In nearly every soldering process in electronic industry, flux, acidic rosin, is used to remove oxides in order to achieve good bonding. Fluxless bonding process, that does not need flux, is made possible by proper design of bonding media and environment. The Ag-In system will be presented to demonstrate the fluxless principle. In contrast with such soldering process, solid state bonding does not involve any molten phase. Ag is chosen for this study because it has the highest electrical conductivity and thermal conductivity among all metals. It is shown that Ag can be bonded directly to copper (Cu) at 250°C. It can also be bonded to gold. Using Ag as bonding medium, Si chips coated with thin Cr/Au have been bonded to Cu substrates. The resulting structure looks like Si/Cr/Au/Ag/Cu. At present, nearly all large Si chips are packaged in flip-chip configuration, with solder bumps connecting the active surface of the chip to the packaging substrate. These bumps are made of Tin(Sn)-rich solder. When the bump diameter shrinks down to 50μm, many problems, such as intermetallic growth, bump bridging, resistance, etc., may arise. These are caused by fundamental limitations and cannot be overcome by process modifications. So, we turned to pure Ag and have demonstrated 15μm Ag interconnect columns between Si chips and Cu with a pitch of 40μm. This presentation will discuss ten potential advantages of the Ag flip-chip technology, when compared to the popular solder-based flip-chip interconnects, in detail.

Metallurgy for high temperature SiC die attach involves the substrate metallization, die metallization, and die attach material. This paper examines off-eutectic Au-Sn as the die attach alloy with a PtAu thick film metallization on AlN substrates. A pure Au thick film layer was printed over the PtAu thick film layer. The SiC backside metallizations evaluated were Ti/TaSi/Pt/Au and Cr/NiCr/Au. Die shear tests were performed after aging at 500°C and after thermal cycling. The shear test results and failure surface analysis are discussed. Nanoparticle Ag and liquid transient phase bonding with Ag based metallurgies have been proposed for high temperature die attach. Data on the migration of sintered nano-particle Ag and thin film Ag dc bias during storage in air at 300°C and 375°C are presented. Migration of Ag is a potential failure mechanism for Ag based high temperature metallurgies.

Silicon-on-insulator (SOI) integrated circuits have been demonstrated for use at temperatures up to 300 °C. However, to build functional electronics, multiple devices must be interconnected to provide the desired functionality. A system-in-package approach has been developed using thick-film technology on Si3N4 ceramic substrates. Si3N4 has a near coefficient-of-thermal-expansion match to Si and a higher flexural modulus than Al2O3, which is commonly used for thick-film applications. The conductor metallization is Au. For 300 °C operation, eutectic Au-Ge die attach was used with a Ti/Ti:W/Au backside die metallization. After 3000 h at 325 °C, the mean die shear strength decreased from 3.96 to 3.33 kg/mm2, a decrease of only 16%. Formation of Au-Si-Ge ternary eutectic (melting point 326 °C) was observed and limits the use of Au-Ge die attach to 300 °C. SOI dies typically have Al wire bond pads that are not compatible with Au thermosonic wire bonding for high-temperature applications. Two plating processes have been examined: electroless Ni/immersion Au/electroless Au and electroless Ni/electroless Pd/immersion Au. The plating processes provide a barrier layer (Ni) and a wire-bondable finish (Au or Pd-Au) over the Al wire bond pads. After 10 000 h at 300 °C, the wire pull force for the Ni/Au samples decreased by ~30% due to annealing of the Au wire, while the ball shear force increased by ~35%. The daisy-chain electrical resistance remained relatively constant. For the Ni-Pd-Au samples, after 2000 h at 320 °C, the ball shear force remained constant or increased slightly, the wire pull force decreased by ~25% due to annealing of the Au wire, and the daisy-chain resistance remained relatively constant. After 3000 h, however, cratering of the Si wire bond pad was observed corresponding to some first bond pad lifts and increased daisy-chain resistance. Optimization of the wire-bonding parameters for bonding to the harder Ni/Pd/Au bond pad is required to eliminate cratering.

A hermetic, multichip power package for silicon carbide devices that will operate in a 200°C ambient and switch 50 to 100 amps has been developed. The Al2O3/MoCu structure, upon which the SiC JFETs and diodes have been attached, was designed in a manner to hermetically seal the device areas. Details of the materials and processes used to fabricate the package are discussed. Die attach, ribbon bonding and lid attach are also described.

The microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolving when exposed to isothermal aging and/or thermal cycling environments. In our prior work on aging effects, we have demonstrated that large degradations occur in the material properties (stiffness and strength) and creep behavior of Sn-Ag-Cu (SAC) lead free solders during aging. These effects are universally detrimental to reliability and are exacerbated as the aging temperature and aging time increases. Conversely, changes due to aging have been shown to be relatively small in conventional Sn-Pb solders. Aging effects for lead free solder materials are especially important for the harsh applications environments present in high performance computing and in automotive, aerospace, and defense applications. In the current investigation, we have extended our previous studies to include a full test matrix of aging temperatures and SAC lead free solder alloys. In an attempt to reduce the aging induced degradation of the material behavior of SAC solders, we are also exploring various doped SAC-X alloys. These materials are SAC solders that have been modified by the addition of small percentages of one or more additional elements (X). Using dopants (e.g. Bi, In, Ni, La, Mg, Mn, Ce, Co, Ti, Zn, etc.) has become widespread to enhance shock/drop reliability, wetting, and other properties; and we have extended this approach to examine the ability of dopants to reduce the effects of aging and extend thermal cycling reliability. The effects of aging on mechanical behavior have been examined by performing stress-strain and creep tests on solder samples that were aged for various durations (0–6 months) at room temperature (25 °C), and several elevated temperatures (50, 75, 100, and 125 °C). Four “standard” SAC alloys have been examined in this work including SAC105, SAC205, SAC305, and SAC405. This selection has allowed us to explore the effects of silver content on aging behavior (we have examined SACN05 with N= 1%, 2%, 3%, and 4% silver; with all alloys containing 0.5% copper). The doped SAC solder materials being considered in our ongoing studies include SAC0307-X, SAC105-X, and SAC305-X. In this work, we will concentrate on presenting the results for SAC0307-X (SAC-X), where X is 0.1%Bi. This alloy has been proposed as a lower cost SAC variation suitable for enhancing drop reliability. For all of the solders, variations of the mechanical and creep properties (elastic modulus, yield stress, ultimate strength, creep compliance, etc.) were observed and modeled as a function of aging time and aging temperature. Our findings show that the doped SAC-X alloy illustrates reduced degradations with aging for all of the aging temperatures considered. The stress-strain and creep mechanical properties of SAC-X are better than those of SAC105 after short durations of aging, and approach those of SAC205 with longer aging times. After long term aging, the SAC-X alloy was found to have more stable behavior than all of the standard SACN05 alloys. Analogous tests were performed with 63Sn-37Pb eutectic solder samples for comparison purposes.