Parallelizing graph algorithms is challenging due to the inherent irregularity of computation, memory access, and communication. The challenge gets exacerbated as newer and different parallel platforms become popular. A domain expert needs to learn multiple programming languages to take advantage of the available underlying hardware. To address this issue, recently, a domain-specific language (DSL) for graph algorithms has been developed, which targets different kinds of hardware, including multi-core, distributed, and many-core architectures. Thus, this DSL generates CUDA, OpenMP, and MPI codes from the same algorithmic specification. At the heart of this versatile translation lies its analysis and transformations operating on a common abstract syntax tree. In this paper, we describe the challenges faced and overcome by this graph DSL’s syntax, code generation, and optimization phases in generating code for different target hardware focusing mainly OpenMP, CUDA and MPI. We evaluate the proposed analyses and transformations using ten large-scale real and synthetic graphs across four fundamental algorithms: PageRank, Betweenness Centrality, Single-Source Shortest Paths, and Triangle Counting. The generated code achieves 1.1 × –100 × speedups over graph-processing frameworks and performance competitive with or surpassing hand-tuned frameworks such as Gunrock, LonestarGPU, Galois, and Ligra. These results show that compiler-driven, graph-specific program analyses can bridge the gap between productivity and performance portability in parallel graph analytics.
Matrix multiplication is at the heart of many applications in AI, scientific computing, and quantum simulations, for which GPUs have been widely adopted due to the immense compute power and hardware acceleration they provide for such computations. In this paper, we explore the performance profile of computing dense matrix–matrix multiplications (GEMM) on GPUs by decomposing the operation into several cascading lower-precision GEMMs and exploiting the then-available overlap between data transfers and mixed-precision compute and measure its performance when compared to standard monolithic or tiled GEMMs. The proposed implementation exploits the high performance of low-precision matrix multiply-accumulate (MMA) operations on modern GPUs and their multi-stream execution capabilities to overlap multiple low-precision GEMMs with data transfers.
Open-source instruction set architectures have greatly helped excel software development. One of the potential architectures is the RISC-V architecture which gained significant attention due to its providing flexibility, extensibility, and scalability for a wide range of computing systems. Optimizing compilers has become a vital tool for enhancing software performance since software is essential to utilizing RISC-V architectures to their fullest potential. The impact of compiler optimization in the RISC-V ecosystem is examined in this review. We go over the significance of compilers, how to optimize them, and a thorough comparison between the GNU compiler collection (GCC) and low-level virtual machine (LLVM) compilers. This study also explores the possibilities and difficulties of incorporating custom instructions into LLVM to take advantage of the special characteristics of RISC-V architectures. It also demonstrates the importance of compiler optimization in enhancing software performance, decreasing code size, and facilitating effective resource utilization in the RISC-V ecosystem through a thorough analysis. In addition, future research directions are identified, such as heterogeneous computing, energy efficiency, performance modeling, compiler-enabled security measures, advanced optimization techniques, support for specialized RISC-V extensions, and domain-specific languages. Investigating these avenues will facilitate the wider adoption and development of this open-source processor architecture by opening the door for more effective and performant software on RISC-V architectures.
Quite often, cache performance is a deterministic factor of throughput, latency, and power efficiency in current multi-core processor architecture specially when it is subject to data-intensive routines in scientific computing, artificial intelligence, and large-scale cloud workloads. Existing machine learning techniques are effective in some cases but often inaccurate or difficult to scale to large workload sets because they require training on the computing platform whereas traditional cache simulators, though accurate, are far too slow to simulate multi-terabyte execution traces. This study proposes CachePredictML, a machine learning system that uses big data to predict the similarities of the cache behavior on multi-core processors. The framework can use a distributed preprocessing pipeline using Apache Spark and HDFS to process up to 4.6 TB of memory access traces of SPEC CPU2017, PARSEC 3.0 and SPLASH-2 benchmarks being run on 16-core Intel Xeon Platinum 8380 and 64-core AMD EPYC 7742 processors. Our Hybrid-Grid solution extracts temporal locality, spatial locality, and reuse distance, and with workload characterization using Random Forest, Gradient Boosting and LSTM networks, plus Graph Neural Networks to model coherence patterns, workload characterization is provided. VO results indicate that CachePredictML delivered 92.34 percent accuracy in prediction, 4.5 percent error in predicting miss ratio, and a 13.4-h reduction in simulation time in contrast to existing state of art ML-based cache predictors. These results demonstrate the power of CachePredictML to speed-up the design-space exploration process, help to tune the cache management policies, and further enable scaleable prediction in a multi-core environment.
Implicit parallel programming models typically give less parallelism control to the programmer, but require less specialised expertise. Explicit parallel models, on the other hand, give much greater parallelism control, but can require significant expertise from the programmer. In this paper, we introduce a novel semi-implicit parallel model, called Elysium, for Idris. Elysium therefore demonstrates semi-explicit parallelism for an emerging class of languages known as dependently-typed languages. These dependently-typed languages encourage safer software via their ability to express strong logical guarantees, in the form of proofs, directly in code. Our semi-implicit approach is based on a process model that uses dependent types to guarantee parallelism properties. We demonstrate how we can use this semi-implicit process model to build common algorithmic skeletons, including farms, pipelines and divide and conquer skeletons. We evaluate our process skeleton approach on a number of examples, achieving speedups of up to 22 on a 28-core machine.
