Gate-level power estimation based on foundry-supplied standard cell libraries is a common analysis step during digital design. Surprisingly little is known about the accuracy of this approach and the suitability for different circuit types. At the same time, commercial tools implementing this approach are employed broadly and often regarded as the reference when comparing estimation methodologies on higher levels of abstraction. This work evaluates the suitability and accuracy of gate level power estimators for combinatorial circuits of different logic depths in order to test the ability of handling real gate delay effects. While the basic methodology leads to estimation errors of up to 32 % for the tested circuits, by various improvements in the work flow the accuracy can be improved at the cost of longer runtimes. Apart from recommendations on improving accuracy this work identifies shortcomings in the established approach and highlights circuit characteristics that tend to influence estimation accuracy.
Phoenix MapReduce is a programming framework for multi-core systems that is used to automatically parallelize and schedule the programs based on the MapReduce framework. This paper presents a novel reconfigurable MapReduce accelerator that can be augmented to multi-core SoCs and it can speedup the indexing and the processing of the MapReduce key-value pairs. The proposed architecture is implemented, mapped and evaluated to an all-programmable SoC with two embedded ARM cores (Zynq FPGA). Depending on the MapReduce application requirements, the user can dynamically reconfigure the FPGA with the appropriate version of the MapReduce accelerator. The performance evaluation shows that the proposed scheme can achieve up to 2.3x overall performance improvement in MapReduce applications.
Next Generation Sequencing technologies produce huge amounts of short reads consisting randomly fragmented DNA base pair strings, while assembling poses a challenge on the mapping of short reads to a reference genome in terms of both sensitivity and execution time. In this paper, we propose a many-core hardware acceleration platform for short read mapping based on hash-index method, which benefit from a distributed memory interface with 3D-stacked architecture for local memory access. Our design provides an amazingly 45012 times speedup over software approach for single end short reads and 21102 times for paired end reads, while also beats similar single FPGA solution for 1466 times in case of single end reads.
Power consumption has become one of the major concerns in embedded systems design, especially for mobile devices, which integrate many applications leading to a high power consumption. In this context, designers have the challenge to identify power issues early in the design flow and to explore the largest possible space of power-efficient solutions. In this paper, we present a Model Driven Engineering (MDE) approach for early power-aware Design Space Exploration (DSE). This approach is based on a high-level modeling of power estimation and dynamic management aspects targeting an automatic generation of the corresponding simulation code. It was implemented in the DSE toolkit TTool by integrating power concepts in its DIPLODOCUS UML profile. The existing C++ simulation code generator was extended in order to integrate power estimation. The main objective of this article is to illustrate the potential of our approach through an MPEG-2 case study. The proposed high-level power modeling concepts were used to target two different platforms for the implementation of an MPEG-2 decoding application. The processor power estimates obtained from simulations were compared to real board measurements. This comparison showed that our MDE approach is capable of obtaining results that can be used to make early power-efficient design decisions.
Simulation techniques cannot cope with the distributive and reactive nature of Network on chip (NoC) architectures very well and thus compromise on the accuracy of the analysis results. Formal verification has been used to overcome these challenges but, to the best of our knowledge, has been mainly used for the verification of packet-switched NoC's. The main focus of this paper is on the formal verification of circuit-switched NoC's, which provide a dedicated channel for all communications with full bandwidth and thus are found to be more efficient than packet-switched NoCs in many contexts. In particular, the paper presents a generic methodology for the formal verification of circuit-switched NoC using the SPIN model checker. The proposed methodology provides generic modelling guidelines and identifies some properties, including deadlock freedom, starvation freedom, mutual exclusion and liveness, that are quite useful in the context of circuit-switched NoC. For illustration purposes, we use our methodology to verify the programmable NoC (PNoC) architecture, which is one of the most widely used circuit-switched NoC.
