The development of compact, energy-efficient Edge AI (artificial intelligence) systems and their MCUs has increased the demand for arithmetic units that deliver both higher accuracy and low power consumption. Posit arithmetic, introduced in 2017 as an alternative to IEEE 754 floating-point, provides comparable accuracy with a smaller memory footprint. Its tapered precision reduces relative error across the orders of magnitude, making low-bit posit formats especially effective. The accuracy of posit arithmetic, however, depends on the exponent size (es), which controls its error characteristics. In this paper, we hypothesize that dynamically adjusting the es can further improve accuracy. To validate this idea, we propose a posit arithmetic unit (PAU) capable of flexibly selecting optimized es values for input and output posit values. As a result, the proposed design achieves higher accuracy within appropriate numerical ranges compared to standard posit formats. We implement and evaluate the design in both software and hardware. In software, PolyBench results show that our PAU reduces the mean relative error distance (MRED) by 45.19% compared to the standard posit. We also develop a CUDA C++ extension to integrate the proposed PAU into neural network models, demonstrating improved performance over standard posit and IEEE 754 floating-point in AI workloads. For hardware validation, we integrate the proposed PAU into a DLX processor and develop a custom C compiler and posit instructions utilizing Synopsys ASIP Designer. Finally, the processor design completed target-process post-layout sign-off using Samsung’s 28 nm low-power process, thereby verifying the physical implementation feasibility of integrating the proposed PAU into a complete processor architecture. The corresponding post-layout EDA reports provide estimates of area, power, and maximum clock frequency.
The Chips-JU (ex KDT-JU) Resilient Trust project focuses on end-to-end security of Internet-of-Things processing chains with a focus on strong exploitation for Small and Medium Enterprises. This vision is realized by developing specialized hardware to establish trust in-between a network and a wall of resilience even against new attack methods such as post quantum attacks and AI-based attacks. The architecture of the secure processing chain is carefully built after threat modelling, asset identification, risk analysis, security objectives and requirements definition. The project aims at significantly mitigating the major risks to enable IoT5.0. Solutions are developed to ensure end-to-end security by boosting resilience and trust along different key supply chains of IoT devices. This paper introduces the project by outlining its motivations and objectives, describing its organization into Work Packages and Use Cases, and summarizing the main results achieved so far.
In image processing pipelines, the complex interaction between operations and their hyperparameters creates an exponential design space where manual optimization is often infeasible. This challenge is magnified in Field-Programmable Gate Array (FPGA) implementations, where achieving an optimal trade-off between conflicting metrics — specifically output quality and hardware resource utilization (LUTs, Flip-Flops, and BRAM) — is critical for system integration. Standard heuristics often fail to navigate these non-linear dependencies effectively due to the structural complexity of the computational graphs. This paper introduces GENIO, a framework designed for High-Level Synthesis (HLS)-based pipelines. GENIO employs a structured representation of pipeline configurations that captures both topology and parameterization, enabling flexible exploration of compositional design spaces under hardware constraints. Within this framework, a Structural Genetic Programming (SGP) strategy is proposed to efficiently navigate the search space. A comprehensive comparative evaluation against NSGA-II, MOEA/D, Particle Swarm Optimization, and reinforcement learning–based strategies demonstrates that the proposed structural evolutionary approach attains competitive Pareto-front quality while exhibiting markedly faster convergence under identical synthesis budgets. In particular, near-optimal configurations are identified approximately 3.2 times earlier than with dominance-based multi-objective algorithms, highlighting its practical advantages in synthesis-driven optimization environments.
