Peak limiting current mode control method is analyzed focusing regions where period-1 limit cycle operation is unstable. It is shown that in these regions two operation modes might occur: higher period number discontinuous conduction mode, and unstable limit cycle continuous conduction mode. Mode boundaries are derived. The analysis is preformed applying both analytical and numerical techniques. The diagrams presenting the converter output current, the period number, and the converter averaged model open loop stability are presented.
Integrated Voltage Regulators (IVRs) have become a viable solution for microprocessor's power delivery. The active parts of the most recent IVRs are built in deep-submicron CMOS technologies and use stacked transistors to allow for the use of advanced low voltage devices with superior switching performance compared to the higher voltage long-channel devices. This paper evaluates three different topologies of CMOS half-bridge converters with respect to efficiency, implementation effort, suitability for on-chip integration, and multiphase applications: the conventional half-bridge converter, the half-bridge converter with conventional Active Neutral Point Clamping (ANPC), and a half-bridge converter with a modified circuit to achieve ANPC. In-depth analysis of the transient processes during switching for all three converters, based on Cadence simulations, reveal that both half-bridge converters with ANPC achieve proper balancing of the blocking voltages of the main transistors and are capable to attain similar efficiencies of 93% at an output power of 200 mW, input and output voltages of 1.6 V and 0.8 V, respectively, and a switching frequency of 150 MHz, which is 1% higher than the one attained with the conventional half-bridge converter. Of the two ANPC half-bridge converters, however, the proposed topology allows to completely turn off its entire power stage or parts of it, features less efficiency sensitivity to variations of dead-time, and achieves the peak efficiency at relatively higher dead-time values. These qualities render the proposed topology particularly suitable for multiphase systems and low load operation.
Ripple-based controls can strongly reduce the required output capacitance in PowerSoC converter thanks to a very fast dynamic response. Unfortunately, these controls are prone to sub-harmonic oscillations and several parameters affect the stability of these systems. This paper derives and validates a simulation-based modeling and stability analysis of a closed-loop V 2Ic control applied to a 5 MHz Buck converter using discrete modeling and Floquet theory to predict stability. This allows the derivation of sensitivity analysis to design robust systems. The work is extended to different V 2 architectures using the same methodology.
