This article introduces a timing optimization approach for wide input voltage range boost converters operating in the Boundary Conduction Mode (BCM). Based on a time-domain analysis of the transient converter waveforms during the deadtime, this work describes the required timing scheme to achieve the optimal Zero Voltage Switching (ZVS) turn on condition for the low-side transistor, in which the driving voltage toggles exactly when the switching node voltage becomes null. The proposed approach consists in optimizing simultaneously the duration of the negative inductor current extension time and the deadtime, so as to achieve optimal ZVS with minimal inductor current ripple. The approach only requires input and output voltage sensors and a Zero-Current Detection (ZCD) circuit, already present in ordinary BCM converters, and is proven to accurately predict the optimal timing parameters. The optimization approach is implemented on a microcontroller, and experimental results on a synchronous boost reveal that the on-line timing adjustment enhances the converter efficiency by up to 1.1%, and preserves the optimal ZVS operation also in transient conditions. Its simple implementation and performance improvement make this approach suitable for wide-range step-up applications.
This paper analyzes a conventional finite control set model predictive control (FCS-MPC) for the current control of single-phase LC-filtered grid-connected converters under distorted grid voltage conditions. The prediction model and the cost function are kept unchanged, so the contribution is analytical and not algorithmic. An analytical formulation is developed to capture how synchronization errors and voltage harmonics affect the predictive model and cost function. It is shown that phase estimation inaccuracies propagate into the control law, leading to degraded current quality and suboptimal switching decisions. The current-tracking error is written as the sum of a term originating in the finite switching set, a term originating in the grid-voltage harmonics, and a term originating in the phase-estimation error, which makes explicit the path by which a synchronization error confined to the reference-generation stage still reaches the switching-state selection. Three synchronization structures, a sine-multiplier PLL, a Notch-PLL and a SOGI-based Orthogonal Signal Generator Phase-Locked Loop (OSG-PLL), are used as controlled sources of phase-estimation error to exercise the derived expressions. Experimental results validate the analysis, demonstrating that synchronization significantly influences total harmonic distortion (THD) and control robustness. The OSG-PLL holds THD below 6% in every tested condition, whereas the sine-multiplier PLL reaches 38% to 54%, an ordering that the derived expressions predict. A controlled voltage-sag test following IEC 61000-4-11 completes the assessment under a non-periodic grid event.
The notably advantageous characteristics of Wide Band Gap (WBG) materials like Silicon Carbide (SiC) have been the primary impetus behind the shift towards WBG-based power modules across a variety of application sectors, like Electric Vehicles (EVs). However, to harness the full capabilities of SiC, power module packaging must simultaneously minimize parasitic inductance and thermal resistance, which conventional Single Side Cooling (SSC) structures fail to achieve. Double Side Cooling (DSC) packaging addresses the thermal limitation, but reaching low and ultra-low parasitic inductance within a DSC structure remains a substantial design challenge. This paper undertakes a comprehensive review of DSC SiC-based power modules specifically developed to achieve low and ultra-low parasitic inductance. Initially, the paper delves into the constraints of the SSC methodology and the complications linked to parasitic inductance. Subsequently, a detailed categorization, in-depth analysis, and comparison of various DSC packaging strategies and techniques are presented, evaluating voltage and current ratings, parasitic inductance, size, and other critical attributes, along with the advantages and disadvantages of each. A comparative analysis of these modules is then conducted using a proposed Figure of Merit. Finally, potential future directions aimed at achieving enhanced performance for DSC SiC power modules are presented.
This paper presents a general method to estimate the root mean square (RMS) of currents and voltages within a switching converter using matrix manipulation of its state-variable representation without having to generate waveforms prior to RMS evaluation. The method uses cyclic-mode analysis of the state-variable model and the multi-dimensional shooting method to determine the steady-state operating conditions of a converter, and then applies the new technique to estimate the RMS of the states. Although applied to resonant converters in the paper, the work has general applicability; it is not restricted to a particular converter topology and can be applied to arbitrary-order state-space models. This generality distinguishes the proposed method from previously reported lower-order or converter-specific treatments. The viability and accuracy of the method is verified for an LLC converter through comparison with SPICE simulation, first-harmonic approximation and experimental measurements.
The finite control set (FCS) strategy is well established in predictive control schemes for three-phase induction motors (IM) fed by two-level voltage source inverters (VSI), the theoretical analysis is crucial to ensure proper operation under variation factors such as parameter mismatch in inductances and resistances, inaccuracies in the mathematical motor model, and diverse speed-reference profiles. For this reason, this work proposes a Lyapunov-based predictive current control approach with Discrete-time integral action (LFCS-DTIA) in the d-q reference frame for induction motor drives (IMD), thus ensuring control stability and improving performance against disturbances such as quantization and parameter errors. The proposed controller achieves robust performance under constrained and conditioned test scenarios with a simple block that incorporates the current errors and, in conjunction with an integral gain, adds a correction term to the predictive voltages to be evaluated against the inverter voltage vectors. This represents an advantage and provides flexibility in the voltage-based cost-function formulation. Experimental tests were conducted to validate the stability analysis and the integration of the DTIA component compared to the PCC, demonstrating acceptable evaluation metrics such as computational burden of 51.35%, phase A current total harmonic distorsion (THD) of 6.8%, synchronous current errors under 0.56 A for parameter mismatch of inductances, and speed of 7.8 rpm, then for resistances of under 0.21 A and speed of 6.4 rpm in steady-state and dynamic operating conditions.
