A 2D-DCT Processor Using One-Time-Programmed Floating-Gate Transistor Array for Processing-in-Sensor Architecture

The widespread deployment of resource-constrained intelligence visual Internet of Things (IoT) edge devices has driven an urgent demand for low-power, high-fidelity image compression solutions. The conventional off-sensor compression approach incurs significant quantization energy overhead, digital memory burden, and data transform latency. To address this issue, this brief presents a 2-D discrete cosine transform (2D-DCT) processor suitable for a processing-in-sensor (PIS) architecture, utilizing a one-time-programmed (OTP) floating-gate transistor (FGT) array as the DCT computing unit (CU). The proposed 2D-DCT processor allows image data to be compressed before digitization, significantly reducing the analog-to-digital converter (ADC)’s quantization overhead and the bandwidth of digital data transmission. The prototype chip is fabricated in a 65 nm flash technology. The proposed 2D-DCT processor was integrated with a $32\times 32$ analog image sensor array to build a PIS system for evaluation. Compression results show a peak signal-to-noise ratio (PSNR) ranging from 29.52 to 32.14 dB and a structural similarity index (SSIM) ranging from 0.934 to 0.973, with a PSNR exceeding 24.3 dB at an $8\times $ compression ratio (CR), indicating high image compression quality. The constructed PIS system achieves a maximum processing frame rate of 398 fps, with a power consumption of $7.06~\mu $ W of the 2D-DCT processor, leading to an energy efficiency of 17.32 pJ/pixel.