With technology scaling and design complexity increasing, glitch-induced dissipation has become nonnegligible in the dynamic power of digital circuits. In ASIC designs, glitch optimization is commonly realized through gate-level or netlist-level structural refinements, whose ability to achieve substantial power reduction with minimal circuit modifications depends on accurately identifying critical cells with high glitch-power impact. However, existing analysis methods misdirect optimization toward less-critical cells, because effective glitch-generation sources are not distinguished and glitch-induced power contribution is incompletely assessed. To address these limitations, this brief proposes a simulation-based glitch analysis and optimization framework. First, a waveform-analysis-based glitch classification algorithm rigorously distinguishes intrinsic glitch generation from propagation, resolving glitch-source misidentification. Then, the holistic glitch-power contribution (HGPC) attribution framework decomposes aggregate glitch-induced power and attributes both self-consumed and downstream propagation-induced components to effective sources, explicitly incorporating glitch-induced internal power ignored by conventional methods. Finally, a signoff-verified greedy engineering change order (ECO) gate downsizing framework validates the proposed analysis method in postlayout optimization. Experiments on several glitch-intensive benchmark circuits using 22-nm CMOS technology demonstrate average reductions of 32.9% in glitch power and 17.2% in total power, with only 11.08% of cells modified, significantly outperforming existing simulation-based methods.
Modern automotive systems require adaptive mechanisms to handle both accidental faults and security threats at runtime. While hardware performance counter (HPC)-based anomaly detection has shown promise in RISC-V platforms, detection alone is insufficient; identifying anomalies without an effective response cannot prevent system failures or security breaches. In safety-critical environments, timely mitigation is essential to preserve system reliability and safety. To bridge this gap, this article proposes a deep reinforcement learning (DRL)-based anomaly mitigation approach that learns adaptive recovery policies from HPC observations, building on prior HPC-based anomaly detection for RISC-V platforms. The problem is formulated as a Markov decision process (MDP) where the DRL agent selects among three recovery actions: advance, restart, or backtrack. The DRL agent is trained on benchmarks running in FreeRTOS with injected faults and subsequently deployed as the safety-critical performance-counter adaptive control engine (SPACE). To satisfy hard real-time constraints, SPACE implements the trained DRL agent on a dedicated SiLago dynamically reconfigurable resource array (DRRA) fabric. Compared to software-based execution on general-purpose RISC-V processors, which severely violates system deadlines, the hardware-accelerated SPACE framework achieves strictly deterministic inference that is over three orders of magnitude faster. Furthermore, it provides critical physical and temporal isolation from the main CPU workloads while maintaining a minimal silicon footprint up to $17\times $ smaller than high-performance out-of-order (O3) cores.
Fully homomorphic encryption (FHE) enables computation on encrypted data without decryption. This makes FHE a valuable privacy-preserving technique applicable in fields such as private machine learning (ML). FHE achieved unlimited homomorphic operations on ciphertext by periodic bootstrapping, which is highly time-consuming. To accelerate FHE, various hardware accelerators have been proposed. However, most FHE accelerators rely on massive on-chip memory to mitigate the off-chip memory bandwidth bottleneck, resulting in a large chip area. We propose WestLake, a memory-efficient accelerator for FHE. To reduce on-chip memory size, we make efforts on algorithmic optimizations, data scheduling, and architectural design. First, we propose several algorithmic optimizations that reduce both on-chip memory size and off-chip memory access. Second, we devise a memory-efficient dataflow for bootstrapping, which leverages the overlapping between computing and data transfer, maximizes data reuse by reordering operations, and balances on-chip memory size and off-chip bandwidth requirements. Finally, we propose WestLake architecture, which features tailored function units (FUs) for primary FHE operations and integrates our algorithmic optimizations and memory-efficient dataflow. WestLake reduces resource usage by enabling a single unit to handle two primary FHE operations (base conversion (BConv) and element-wise operation). In contrast to the state-of-the-art Cheon–Kim–Kim–Song (CKKS) accelerator SHARP, which used 198 MB on-chip memory, WestLake only utilizes 80 MB on-chip memory. Compared to SHARP, WestLake achieves a speedup of $1.7\times $ in geometric mean with $2.1\times $ smaller chip area and $1.6\times $ less power consumption.
This study extensively examines the power, performance, and area benefits of backside signal intracell routing for Angstrom nodes. For effective backside signal implementation, wrap-around contact (WAC) is applied to reduce contact resistance. Since backside metal layers with narrow widths substantially increase process cost, only a single MB1 layer is used for backside intracell routing. As the backside power linewidth decreases, parasitic capacitance is reduced, improving single-cell performance, while the IR drop remains sufficiently low at a small micro-bump pitch. Because the proposed scheme keeps cell pins on the frontside, only cells containing relocatable nonpin metals can benefit; thus, cells such as INVx1 show no benefit. The proposed routing reduces Miller capacitance and improves the cell-level energy-delay product (EDP), with more pronounced benefits in complex cells such as DFF. At the chip level, backside intracell routing alleviates routing congestion, reducing frontside intercell wire length by 4.1%–6.8%. The wire-length reduction is more pronounced in macro-containing designs, such as the Rocket benchmark, due to their higher routing complexity. In the Rocket benchmark, the conventional design exhibits 19–73short violations, whereas backside signal intracell routing reduces them to nearly zero. Backside intracell routing also decreases the number of inserted repeaters. Furthermore, backside signal intracell routing provides a thermal benefit by mitigating the chip temperature. Overall, backside signal intracell routing improves the power-delay product by 4.3%–14.2% across all benchmarks by combining cell-level optimization with routing-congestion and chip temperature reduction. This study provides practical guidelines for the characteristics and benefits of backside signal intracell routing.
Sparse matrix-matrix multiplication (SpMM) is critical for graph analytics and learning tasks, yet its irregular sparsity poses challenges for hardware acceleration. Traditional static dataflows fail to adapt to local sparsity variations, causing load imbalance. We introduce SpMM-GO, a hybrid FPGA accelerator integrating Gustavson’s algorithm and Outer-Product dataflows. A Dynamic Density-Aware Dispatcher assigns tiles at runtime: sparse tiles go to Gustavson dataflow PEs to minimize reduction overhead, while dense tiles go to Outer-Product dataflow PEs to maximize computational density. To ensure load balancing, we employ a feedback-driven scheduling algorithm that adjusts dispatch thresholds based on PE workload. Experiments show SpMM-GO achieves a geometric-mean speedup of $10.5\times $ (up to $25.4\times $ ) over a CPU baseline at the reference 2S+2D configuration, demonstrating the high efficiency and adaptability of our dynamic hybrid dataflow architecture.
As the thermal issue in integrated chips becomes increasingly severe, thermal sign-off and thermal management become more important for performance and reliability. Thermal libraries provide an offline approach to avoid time-consuming real-time thermal simulations. However, thermal library characterization under multicorner scenarios for thermal sign-off is a computationally expensive task. This work decouples the thermal resistance of a standard cell into two components: the thermal critical transistors that dominate heat generation and dissipation, which are corner-invariant and determined by the cell topology, and the transistor thermal resistances, which are corner-dependent. Based on this insight, we propose a fast multicorner thermal library characterization methodology, which significantly enhances efficiency through the reuse of thermal-critical transistor information. The characterized thermal library can be seamlessly integrated into mature electronic design automation (EDA) toolchains, enabling rapid full-chip, standard cell-level thermal assessment in both steady-state and transient conditions, while accounting for thermal coupling and thermal relaxation effects. The proposed methodology reduces the thermal library characterization time for multicorner thermal libraries from several weeks to 1 h. The accuracy of the proposed thermal assessment methodology has been validated through finite element simulation, and its full-chip thermal evaluation speed is 3.8 times faster than HotSpot.
Boolean satisfiability (SAT) stands as a fundamental problem that underpins a wide spectrum of electronic design automation (EDA) and artificial intelligence (AI) tasks. While the Ising model provides a powerful alternative for SAT solving, existing Ising-based solvers suffer from excessive storage overhead and complex mapping topologies. This brief presents a novel sparsity-aware hierarchical-topology-driven Ising annealing processor (SHAP) to address these challenges for 3-SAT problems. Benefiting from the proposed hierarchical Ising topology and its customized simulated annealing (SA) algorithm, the solving process is efficiently accelerated. Furthermore, by utilizing the hybrid coefficient management strategy, the memory overhead is significantly reduced. The proposed processor is simulated with a postlayout netlist in a 28-nm CMOS technology with an operating frequency of 200 MHz. The proposed design is validated using the SATLIB and self-generated dataset, with problem sizes of up to 50 variables and 218 clauses. It achieves a 97% solvability rate for 30–126 instances. While the benchmark MiniSat guarantees 100% solvability, our design delivers a $5\times $ speedup on successfully solved trials.
This article presents an ultralow power standalone under-voltage lockout (UVLO) circuit for always-on power monitoring in low-power electronic systems. Unlike conventional UVLO circuits that rely on a resistive divider for supply-voltage sensing and an additional voltage reference, the proposed design utilizes a diode-connected transistor-based voltage sensor that provides voltage scaling while limiting current consumption after the UVLO is triggered. Furthermore, a compact two-transistor reference bias is employed, and the bias current for the comparator is reused from the current-limited supply voltage sensor, enabling a fully self-biased architecture without requiring additional bias circuitry for the comparator or reference generator. The proposed UVLO is implemented in a 180nm CMOS process, and measured results show UVLO triggering voltages of 2.38 and 2.19V with 0.19V hysteresis. The proposed circuit consumes an average current of 10.9nA and a minimum current of 8nA at a 5V supply across 16 samples, achieving an $862\times $ reduction in current compared to operation without the current-limiting mechanism.
Advanced process scaling has introduced significant reliability challenges where microprocessors exhibit highly dynamic sensitivity to transient faults across varying operating environments and application phases. Conventional static lockstep architectures impose rigid redundancy levels, leading to either permanent resource wastage or an inflexible reliability boundary. This article presents an instruction-driven dynamically reconfigurable lockstep architecture that provides a continuum of capabilities for requirement-defined redundancy. Leveraging custom RISC-V instruction set architecture (ISA) extensions, software modulates hardware resources across six operational modes, ranging from high-performance symmetric independent execution to high-reliability triple-core lockstep (TCLS). This reconfiguration is managed by a lockstep controller and an access switching unit (ASU) matrix, achieving mode transitions within a deterministic window of 3–10 cycles. Implemented on 28-nm CMOS, the triple-core CV32E40P cluster achieves 617MHz. Compared to a standalone baseline core, the architecture occupies $3.18\times $ area and consumes $2.64\times $ power, with a marginal frequency penalty of 4.94%. Fault injection campaigns confirm a bounded recovery latency of less than 115 cycles across all redundancy modes. This framework enables software-defined alignment of hardware reliability with runtime requirements.
Deep spiking neural networks (SNNs) have gained significant attention in the current landscape of neural computing, primarily due to their remarkable energy efficiency and capability to perform complex computational tasks. This article presents the hardware implementation of a residual SNN (RSNN) architecture featuring four layers equipped with residual connections. We propose a novel edge-based data encoding scheme to enhance RSNN’s efficiency. This encoding scheme significantly accelerates the training and inference processes by $5.2\times $ and $3.1\times $ on an Nvidia A100GPU having 80GB of memory, compared to conventional encoding schemes, rate, latency, and delta encoding on the MNIST, fashion-MNIST (FMNIST), and KMNIST datasets. Moreover, it drastically reduces memory usage and energy consumption by $\sim \!37\times $ and $\sim \!4.3\times $ . In addition, this article proposes two distinct hardware implementations of the proposed RSNN using an AMD VCK190field-programmable gate array (FPGA): sequential RSNN (SRSNN) and sequential–parallel RSNN (SPRSNN). SRSNN uses $\sim \!\!3\times $ fewer hardware resources than SPRSNN on an FPGA. In contrast, SPRSNN exhibits $10.6\times $ and $2\times $ lower latency and power consumption than SRSNN. The proposed FPGA-based realizations show an accuracy of 98%, 89%, and 95% on the MNIST, FMNIST, and KMNIST datasets, while reducing power consumption by $3.2\times $ . They are at least $3\times $ more resource efficient than contemporary SNN architectures with comparable latencies.
Field-programmable gate array (FPGA)-based acceleration for 3-D object detection has attracted significant attention due to its potential for high efficiency and low latency. However, existing fully sparse 3-D Transformer accelerators suffer from inefficient dataflows and limited parallelism, mainly caused by irregular sparsity patterns and global attention dependencies. To address these challenges, this work introduces the fully sparse Transformer pipeline (FST-PIPE). FST-PIPE adopts a hybrid-grained pipeline that integrates coarse-grained inter-layer streaming with fine-grained intra-operator parallelism, and incorporates a memory-efficient storage design to maximize parallelism and memory efficiency. FST-PIPE is enabled by restructuring global sparse attention into an axis-aligned representation through the proposed AxisFormer block, thereby enabling efficient modeling of long-range dependencies among spatially distant nonempty voxels. Furthermore, this work introduces a length-aware pipeline scheduling mechanism to address workload imbalance arising from variable sequence lengths, eliminating pipeline bubbles and sustaining high hardware utilization. Implemented on a ZCU102 FPGA, FST-PIPE achieves 42.59 frames/s with a latency of 23.48 ms and an energy efficiency of 9.5 frames/s/W, providing up to $1.45\times $ higher throughput and around $2\times $ better energy efficiency compared with prior FPGA-based accelerators.
Tensor virtual machine–versatile tensor accelerator (TVM–VTA) stack is an end-to-end deep neural network (DNN) accelerator template known for its high reconfigurability and flexibility. However, baseline TVM–VTA accelerator templates may introduce pipeline and scheduling inefficiencies. Pipelined VTA (PVTA) focuses on the specific execution bottlenecks of the TVM–VTA stack and develops a pipeline-oriented solution across microarchitecture and instruction flow. The proposed architecture redesigns the GEMM and ALU pipelines, instruction flow, LOAD module, and dual-thread dependency mechanism, while maintaining compatibility with the existing software-hardware stack. Implemented on Xilinx ZCU104 FPGA, the proposed PVTA achieves a DSP efficiency of 0.564, delivering $3.9\times $ and $2.54\times $ speedups over the original VTA on ResNet-50 and YOLOv3, with final throughputs of 29.2 and 7.25 fps, respectively. These improvements demonstrate the effectiveness of pipeline-focused optimizations in enhancing VTA’s performance for end-to-end DNN acceleration. Evaluation against representative VTA-based designs shows that PVTA attains the highest reported end-to-end speedup within the VTA framework. Compared to other leading architectures, the proposed approach achieves comparable or higher performance while preserving a high degree of flexibility, enabling VTA to evolve from a research template into a competitive, high-performance end-to-end accelerator.
Two wideband harmonic selection noise-cancelling (HS-NC) RF receiver front-ends are presented, which are capable of supporting 5G new radio (NR) and Wi-Fi 6E applications, and operate from 0.5 to 7.2 GHz. Their architecture employs a differential harmonic selection N-path filter (HS-NPF) with resistive coefficients to avoid voltage gain at harmonic blocker frequencies, and exploits baseband (BB) harmonic recombination blocks to select the desired local oscillator (LO) harmonics, in addition to featuring noise cancelling. It is demonstrated that a conventional feed-forward NPF, two separate resistive HS-NPF down conversion paths, and BB harmonic recombination stages can be configured to select the first LO harmonic in the low-frequency band ( ${\mathrm {0.5-}} {\mathrm {2.4~\text {G}\text {Hz} }}$ ) and the third LO harmonic in the high-frequency band ( ${\mathrm {2.4-}} {\mathrm {7.2~\text {G}\text {Hz} }}$ ). Higher harmonic selection rather than the fundamental helps to reduce the dynamic power consumption and required input frequency of the multiphase LO clock generator at the high-frequency band. The two RF receiver front-ends are fabricated in a TSMC 65 nm CMOS technology. The first receiver (RX1) achieves a harmonic-rejection ratio (HRR) of higher than 44 dB, a minimum in-band noise figure (NF) of 3.4 dB at a 80 MHz BB frequency, and out-of-band (OOB) third-order input intercept point (IIP3) of higher than 9.2 dBm over the entire frequency band of operation, with a power consumption of ${\mathrm {14.5-}} {\mathrm {20.8~\text {m}\text {W} }}$ , including the LO generation circuit. The second receiver’s (RX2) NF is ${\mathrm {3.9-}} {\mathrm {4.8~\text {d}\text {B} }}$ , and in-band IIP3, OOB IIP3, and third and first HRRs are higher than -21.6, 6.7, 42, and 37 dB, respectively. The receiver has a total power consumption of ${\mathrm {11.1-}} {\mathrm {17.4~\text {m}\text {W} }}$ from a 1.2-V supply. The key difference between the two receivers is that the harmonic recombination blocks are employed right after the downconversion in RX1, while a bank of TIAs is used between the downconversion paths and the harmonic recombination blocks in RX2. RX1 provides better performance at the cost of higher power consumption in comparison to RX2.
In this article, we propose a turbo two-bit gradient descent bit-flipping (TTGDBF) algorithm for low-density parity-check (LDPC) codes in nand storage systems. The TTGDBF algorithm introduces an additional bit at each variable node (VN) to represent its “strength,” which is further combined with the turbo flipping mechanism to improve the error-correction capability. To fulfill the high-throughput requirement, the proposed algorithm breaks the separation between the maximum-finding phase and the flipping phase in conventional gradient descent-based algorithms, allowing the codeword bit to be flipped at any time during the decoding process, thereby accelerating the convergence speed and decoding performance. Furthermore, a VLSI architecture is proposed for efficient hardware implementation of the TTGDBF algorithm, which achieves a 55.5% reduction in logic area and a 75.6% increase in throughput compared to the unified penalty GDBF (UPGDBF) decoder. Implemented in the TSMC 65 nm process, the proposed 4KB LDPC decoder can achieve a throughput of 15.87 Gbps with an area of 0.992 mm2, demonstrating high efficiency for high-speed nand storage applications.
Path exploration, localization, and mapping are fundamental capabilities for autonomous microrobots, which require high energy efficiency and low hardware overhead for long-term edge deployment. However, it remains challenging to simultaneously achieve high energy efficiency, high precision, and low latency on energy-constrained robotic platforms. To address the above challenges, this article proposes a brain-inspired metric–topology-fusion reconfigurable GVD-NeuroSLAM hardware accelerator. At the algorithm level, a metric–topology-fusion GVD-NeuroSLAM algorithm is proposed, where a generalized Voronoi diagram (GVD) provides topology-constrained metric estimation to enhance the precision of NeuroSLAM, while NeuroSLAM provides metric-corrected exploration-direction refinement to achieve efficient exploration. At the architecture level, a reconfigurable end-to-end GVD-NeuroSLAM hardware accelerator, MT-REN, is proposed, which integrates a topology-guided LiDAR point filtering module and a metric-guided continuous attractor neural network (CANN) module to reduce redundant exploration energy consumption while improving SLAM precision. At the microarchitecture level, a fast-convergence CORDIC-based configurable coordinate calculation module and a workload-aware reconfigurable dual-mode processing element (PE) cluster are developed to further enhance energy efficiency, hardware utilization, and computational speed. FPGA implementation results show that the proposed MT-REN achieves significantly higher energy efficiency than conventional visual SLAM (VSLAM) accelerators and higher precision with negligible hardware and latency overhead than the state-of-the-art NeuroSLAM accelerator.
This brief presents a low-power single-slope analog-to-digital converter (SS ADC) featuring an LSB-error-suppressed double-data-rate (DDR) counter for CMOS image sensors (CISs). A novel DDR counter is proposed to resolve the least-significant-bit (LSB) error issue in conventional DDR counters. The proposed counter establishes a direct logical relationship between the LSB decision signal and the high-order counter stop signal, thereby suppressing LSB errors without auxiliary calibration. The prototype chip was fabricated in a 180-nm CMOS process. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.28/+0.26 LSB and −1.55/+2.28 LSB, respectively. The nonuniformity of 64-column SS ADCs is within 0.07% (standard deviation) over an input range from 1.0 to 1.9 V. Each column ADC consumes $47.12~\mu $ W while using a 150-MHz clock with dual-edge counting. The presented SS ADC achieves 12-bit resolution with a column-level figure of merit (FoM1) of 1.04 pJ $\cdot \mu $ m/conv.-step and an area-normalized figure of merit (FoM2) of $41.41~\mu $ W $\cdot \mu $ m2/conv.-step.
This brief presents a fully integrated 21-bit incremental $\Sigma $ – $\Delta $ analog-to-digital converter (ADC) with a switched-capacitor bandgap reference (SC-BGR) sharing the same integrator. The SC-BGR and ADC share the same integrator, eliminating the need for a separate summation amplifier and reference sampling capacitors in conventional implementations, which helps reduce low-frequency reference noise and power consumption. Dynamic element matching (DEM) and auto-zeroing are applied to both the bandgap and ADC during the oversampling and residue-counting phases, further suppressing mismatch, offset, and low-frequency noise. The proposed ADC achieves a peak SNR of 118 dB for quasi-static signals at an output data rate of 32 samples/s, with a power consumption of 112 $\mu $ W and an FoM ${}_{\mathbf {S}}$ of 169.6 dB. The measured ADC temperature coefficient (TC) is down to 2.16 ppm/°C, which is comparable to discrete precision bandgap References.
As system-on-chip (SoC) designs continue to scale toward highly heterogeneous multicore architectures, the limitations of global clocking make communication increasingly challenging with lower technology nodes. Asynchronous network-on-chip (NoC) architectures offer an attractive solution for enabling scalable communication in globally asynchronous locally synchronous (GALS) systems. However, the practical adoption of asynchronous routers remains limited due to the design complexity of asynchronous circuits and their limited compatibility with conventional electronic design automation (EDA) tool flows. This article presents HyPA, a hybrid pipeline asynchronous router architecture for NoC communication in GALS-based SoCs. The proposed HyPA router is built on a high-throughput domino-logic pipeline template with a one-hot hybrid data encoding scheme, which facilitates a simple, scalable router architecture while maintaining compatibility with the conventional EDA flow. The HyPA router is implemented using the conventional EDA design flow targeting 65-nm United Microelectronics Corporation (UMC) technology and evaluated through postlayout back-annotated timing and power analysis. The HyPA router, when benchmarked against synchronous routers, showed 62% lower power consumption and an average 85% reduction in energy-per-flit under the same operational conditions. The router achieves a minimum forward latency of 0.8 ns and a throughput of 1.65 GFlits/port/s. The presented HyPA router shows better performance, despite a slight area overhead resulting from its asymmetric layout, when evaluated using a metric-based comparison against recently reported designs. These results illustrate the feasibility of implementing high-performance NoC routers in industrial SoC designs without specialized toolchains.
In the era of Transformers and large language models (LLMs), communication bandwidth has superseded compute capability as the dominant architectural bottleneck. These workloads require frequent aggregated multicast, requiring the simultaneous delivery of distinct data streams to multiple processing element (PE) clusters. Existing network-on-chip (NoC) multicast solutions, however, are largely restricted to identical-data broadcasts, necessitating serialized transfers for heterogeneous data and severely degrading efficiency. We present parallel aggregated connection NoC (PAC-NoC), a novel bandwidth-tapered fat tree NoC that introduces aggregated multicast as its core communication primitive. By codesigning three key components, namely source-side operand aggregation (SSOA), deterministic aggregated communication (DAC), and hardwired slicing (HS), PAC-NoC improves bandwidth utilization and bypasses the complex routing and arbitration logic of conventional NoCs. Our results on Transformer benchmarks demonstrate that PAC-NoC reduces latency by up to 52% and energy by up to 52% over traditional baselines. Even against bandwidth-equivalent competitors with optimized dataflow mapping, PAC-NoC provides significant gains, reducing latency by up to 49% and energy by up to 57%.
Gaussian sample generation (GSG) is a critical component in Monte Carlo (MC) simulation. Conventional hardware GSG architectures have typically been designed under the assumption of uniform random sampling over the entire input domain and aim to minimize correlation between consecutively generated samples. However, MC simulation often employs stratified sampling and related variance-reduction techniques, which deterministically partition the sampling domain. This article presents a stratified GSG architecture tailored for MC simulation, developed under the assumptions of equal-measure strata, equal allocation, and a power-of-two number of strata. By analyzing the inverse cumulative distribution function (ICDF) of the standard normal distribution (SND), we show that the hierarchical segmentation (HS) method admits a reduction ratio of 0.5 in its main segment (MS) structure. Exploiting this property, this article derives a stratified segmentation scheme in which redundant segmentation levels are eliminated when the sampling domain is reduced. Compared with conventional parallel HS-based GSG architectures, the proposed design significantly reduces hardware resources while maintaining identical or lower error. Field programmable gate array implementation results demonstrate up to $21.09\times $ , $2.58\times $ , and $4.71\times $ improvement in throughput per configurable logic block for 16-, 24-, and 32-bit precisions, respectively. Statistical validation confirms that the generated samples preserve the required Gaussian distribution and independence properties. These results demonstrate that incorporating MC-specific sampling characteristics into hardware segmentation fundamentally improves the resource-performance tradeoff of GSGs.
