A per-core clock generator for the eight-core POWER7™ processor is implemented with a digital PLL. This frequency generator is capable of smooth, controlled frequency slewing, minimizing the impact of di/dt. Frequency can be dynamically adjusted while the clock is running, and without skipping any cycles, thus enabling aggressive power management techniques.
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digital phase locked loops,microprocessor chips,power aware computing,digital PLL,eight core POWER7™ microprocessor,frequency generator,per core variable frequency clock generator,power management techniques
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