Thickness scaling of FeFETs with Hf 0.5 Zr 0.5 O 2 (HZO) from 11 down to $4.6\mathrm{~nm}$ is systematically studied in this work in terms of the memory characteristics and the memory window (MW) narrowing mechanism. The HZO thickness scaling leads to low-voltage operation, higher $I_{\text{on}}/I_{\text{off}}$ ratio, lower S.S., and better endurance. It is also found, for the first time, that with reducing cycling voltage the dominant narrowing mechanism changes from MOS interface degradation to ferroelectric fatigue, which can be recovered by a high-voltage pulse. Based on this finding, we propose and demonstrate a method to improve endurance by utilizing this recovery, which is more effective in thinner HZO FeFETs.
The large memory window of $1.8\mathrm{~V}$ at the low write voltage of $2\mathrm{~V}$ is achieved by stacked two nanosheet (NS) gate-allaround (GAA) Ge 0.98 Si 0.02 FeFETs with the channel phosphorus concentration larger than $1\mathrm{E}18\mathrm{~cm}^{-3}$, enabling the erase of GAA FeFET. Isotropic wet etching was used in channel release process. Stacked two NSs have the advantages of reducing cell variation and 2X read current. The stable storage with data retention of $\gt 1\mathrm{E}4$ seconds, linearly extrapolated 10 years, and high endurance $\gt 1\mathrm{E}11$ cycles are also demonstrated. The thermal budget is as low as $400^{\circ}\mathrm{C}$. The stacked NS architecture with high mobility channels makes FeFETs to be compatible with the $2\mathrm{~nm}$ node and beyond.
It is presented the first active-matrix (AM) mini light-emitting diode (LED) driver system for a back-light unit (BLU) that uses a newly proposed 1-pair clock-embedding unified standard interface (USI-B) to reduce EMI and power consumption. The system consists of a pixel driver IC (PDIC) and a pixel IC (PIC). The PDIC transmits 20-bit brightness data to the PIC to control the mini-LEDs. The USI-B, based on clock and data recovery (CDR), has been applied to enhance high-level noise tolerance, long-distance transmission, and EMI reduction. Self-current calibration and offset cancellation in the PIC allow for current accuracy of up to ±1% between PICs. This system can support 16,128 LED local-dimming zones (LDZ) using two PDIC and has a measured EMI level of less than 30dB($\mu$V/m). The PDIC and PIC were fabricated using a 65nm and 130nm CMOS process, respectively.
U-MRAM, an enabler of a diode-selected cross-point MRAM array, is demonstrated using a mature device structure identical to STT-MRAM. U-MRAM exploits the probabilistic switching of thermal fluctuations using a single write voltage. The asymmetric synthetic antiferromagnetic layer (SAF) enables promising UMRAM properties, including low voltage (0.6 V), high speed (10 ns), excellent endurance (>$10^{10})$, and long retention (>10 years) without an external magnetic field. Diode-selected U-MRAM is a strong candidate for future high-density embedded memory.
PowerVia Technology [1] is a novel innovation to extend Moore’s Law scaling by having Power Delivery on the backside. This paper presents the pre & post-silicon findings from implementing an Intel E-Core in PowerVia Technology. PowerVia enabled standard cell utilization of >90% in large areas of the core while showing >5% Frequency benefit in Silicon due to reduced IR drop. Successful Post-Silicon debug is demonstrated with slightly higher but acceptable throughput times. The thermal characteristic of the PowerVia test-chip is in line with higher power densities expected from logic scaling.
This paper presents a switched-capacitor-based integer compute unit in 5nm CMOS that is designed as a drop-in replacement for an equivalent digital unit to improve power efficiency by 2. 5X. Integer multiply-accumulate (MAC) operations are recast as a scaled sum of l-b MACs, where each l-b MAC is performed using a population counter (PPCTR) circuit. Each PPCTR is an enhanced SAR ADC that performs l-b multiplication, D-A conversion, accumulation, and A-D conversion with no loss of precision. The compute unit has 4864 PPCTRs arranged as 64 processing engines, with a total throughput of 104.9 TOPS and 650 TOPS/W power efficiency for l-b MACs.
We present a compact, highly reconfigurable charge-domain analog-FIR (AFIR) filter for high channel selectivity receivers such as BLE, Zigbee, and IoT applications. This architecture demonstrates excellent power-scaling with reconfigurability to different bandwidth and desired stopband rejection. The charge-domain FIR filter modulates both pulse width and transconductance which multiply to generate the charges of the FIR coefficient. Varying both time and transconductance achieves high programmability enabling a wide range of bit-resolution and FIR tap number combinations to achieve a customizable filter response at optimal power. Fabricated in 28nm CMOS, the filter achieves −70dB stopband rejection with a sharp transition and a low power consumption of 0.356mW.
Advances in CMOS technologies have led to the development of continuous-time ΔΣ modulators (CTDSMs) with GHz sampling rates that achieve better than-100dBc linearity and bandwidths above 100MHz. However, at low frequencies (below ~10MHz), their SNDR is limited by 1/f noise, which limits their use in radio receivers intended to cover both the AM and the FM bands. In this work, a multi-path multi-frequency chopping scheme is proposed to suppress 1/f noise, while maintaining interferer robustness, noise, spurious, and linearity performance. Implemented in a CTDSM sampling at 6GHz, it reduces its 1/f noise corner frequency by 22x and achieves −98.3dBc THD, 122dBFS SFDR in 120MHzBW.
This report is the first to demonstrate cryogenic 3D flash memory of 7-bits per cell with the recovery annealing applied repeatedly. We combined 77 K cryogenic operation and epi-Si channel to improve the data retention, read noise, and program noise, and their degradation caused by Program/Erase (P/E) cycles. We further applied $200 ^{\circ}\mathrm{C}$ annealing which recovers performance degradations under appropriate cell Vth conditions. Reliable 7-bits per cell operation can maintain performance and energy efficiency competitive to current QLC and NL-HDD technologies. Co-optimization of process technology, memory operation, and cooling system is a promising solution for future sustainable bit cost scaling.
Although there has been much activity in the development of ultra-low-power analog front ends for edge AI, the low selective frequency accuracy of these front ends causes high training load on the AI part and high-test cost. In this paper, we have developed a new circuit that fundamentally solves these problems by down-conversion. The circuit configuration of the multiplier, harmonic elimination filter, and full-wave rectifier is reviewed from scratch, the ultra-low power converter is downsized and integrated, and the frequency components are converted to a pulse train. The frequency to be analyzed is determined by the local frequency input to the multiplier, and this frequency can be controlled digitally with high precision. Independent of the center frequency, the equivalent Q value can be easily adjusted simply by changing the bias current of the rectifier circuit, resulting in high frequency selectivity and ultra-low power consumption operation. The test chip was fabricated with $0.18 \mu \mathrm{m}$ and operated with a 1.2V supply to output a power pulse stream corresponding to 11 different frequencies from 500 to 5kHz. The total operating power was $1.0 \mu \mathrm{W}$ and the realized equivalent Q-values ranged from 3.6 to 36.
For the first time, we propose selection guidelines for using the front-side (FS) or back-side (BS) power delivery network (PDN) in a $2\mathrm{~nm}$ node. IR drop of various FS and BS-PDN structures have been analyzed for high-performance computing (HPC) and mobile SoC applications. Added process cost (PC) of BS-PDN should be $\lt 5.9\%$ of nanosheet FET (NSFET) based front-side cost for mobile SoCs, but much higher $\lt 10.9\%$ for HPCs, to be cost-effective at similar IR drop.
This paper presents a sub-THz (88-136GHz) full-duplex phased-array transceiver integrating an RF self-interference canceller with differential-feeding full-duplex antennas. The LO phase generation chain controls differential transmitter outputs for the phased-array operation. In the over-the-air measurement, the proposed full-duplex transceiver achieves 6Gb/s in 8PSK and 4Gb/s in 16QAM. The self-interference suppression is improved by 20dB when the self-interference canceller is turned on. The transceiver also achieves a 112Gb/s data rate by wideband amplifiers and the neutralized mixer.
This work describes an electronic skin (e-skin) taxel readout chip in $0.18 \mu \mathrm{m}$ CMOS technology, achieving the highest reported spatial resolution of $200 \mu \mathrm{m}$, comparable to human fingertips. A key innovation is the integration on chip of $\mathrm{a}12 \times 16$ taxel array with per-taxel signal conditioning frontend and spiking readout combined with embedded neuromorphic first-order processing through Complex Receptive Fields (CRFs). The chip has been designed to incorporate a polyvinylidene fluoride (PVDF)-based piezoelectric sensor layer. Experimental results show that Spiking Neural Network (SNN)-based classification of the chip’s spatiotemporal spiking output for input tactile stimuli such as texture and flutter frequency achieves excellent accuracies up to 97.1% and 99.2% of classification accuracy, respectively. This is despite using only a small 256-neuron SNN classifier, a low equivalent spike encoding resolution of 3-4 bits, a sub-Nyquist 2.2kHz population spiking rate, and a state-of-the-art per-taxel (12.33nW) and system $(75 \mu \mathrm{W} -5$mW) power consumption.
This paper proposes an energy-efficient Transformer processor exploiting dynamic similarity in global attention computing. It has three features: 1) A principal-component-prior speculation unit (PCSU) removes 28.4% of redundant computations. 2) A similar-vector tracked computing engine (STCE) saves 42.2% of multiplications. 3) A bit-wise stationary processing element (BSPE) reduces multiplication energy by $1.47\times$. The proposed processor achieves a peak energy efficiency of 77.35TOPS/W. It reduces energy by $2.81\times$ and offers $3.71\times$ speedup compared with the state-of-the-art Transformer processor.
This paper presents a 28nm 1.04pJ/SOP sub-mm 2 spiking and back-propagation hybrid neural network asynchronous olfactory processor enabling few-shot class-incremental on-chip learning for the first time, showing <33.27μW training power budget at 0.55V with gas recognition, concentration estimation, and gas incremental learning tasks. This processor achieves 110.62× and 4.09× energy saving respectively over the state-of-the-art gas recognition and SNN chips.
In this work, we report a monolithically 3D integration of HfZrO x (HZO) ferroelectric FET (FeFET), analog computing-in-memory (CIM), hybrid back-end-of-line (BEOL) CMOS on top of standard Si-CMOS technology, namely M3D-FACT. The 1 st layer is Si CMOS circuits for control logic, and the 2 nd layer is an analog resistive random-access memory (RRAM) array for CIM. The 3 rd layer is a reconfigurable datapath (RCD), consisting of FeFETs with InGaZnO x (IGZO) channel and hybrid CMOS logic based on carbon nanotube (CNT) PMOS and IGZO NMOS. The structure and functions of each layer were verified. Furthermore, a reconfigurable CIM architecture was implemented using the M3D-FACT chip, and the system-level benchmark against its 2D counterpart shows higher energy efficiency in three different network models (6.9$\times $ for VGG-8, 19.2$\times$ for DenseNet-121, and 9.9$\times$ for ResNet-18).
This article introduces a digital FMCW PLL with cycle-slipping compensation scheme and wideband digital-to-time converter (DTC) gain calibration to break the limitation of the maximum trackable chirp slope for two-point modulation (TPM) FMCW PLLs. In addition, FM error is minimized by the proposed back-tracking digital-pre-distortion (DPD) scheme. As far as the authors are aware, the proposed FMCW PLL achieves the widest normalized chirp bandwidth and the fastest normalized chirp slope concurrently while retaining decent chirp linearity.
This paper evaluates Power-Performance-Area (PPA) tradeoffs and integration challenges of three types of backside power connections: Through Silicon Via in the Middle Of Line (TSVM), Self-Aligned Front-to-Back via (BPR) and Backside contact (BSC) for nanosheets at N2 and A14 nodes. From TSVM to BPR to BSC, solid PPA gain s are shown for High Density Logic, at the expense of increased process complexity. While TSVM remains competitive in N27-Track high-performance technology, BSC shows maximal gain s in A145-Track high density node.
In this paper, the most upgraded 4nm (SF4X) ensuring HPC application was successfully demonstrated. Key features are (1) Significant performance +10% boosting with Power -23% reduction via advanced SD stress engineering, Transistor level DTCO (T-DTCO) and MOL scheme, (2) New HPC options: Ultra-Low-Vt device (ULVT), high speed SRAM and high Vdd operation guarantee with a newly developed MOL scheme. SF4X enhancement has been proved by a product to bring CPU Vmin reduction -60mV / IDDQ -10% variation reduction together with improved SRAM process margin. Moreover, to secure high Vdd operation, Contact-Gate breakdown voltage is improved by $\gt 1\mathrm{V}$ without Performance degradation. This SF4X technology provides a tremendous performance benefits for various applications in a wide operation range.
