In-memory computing (IMC) using memristor crossbar arrays offers a promising approach to accelerating neural networks by performing analog computation directly within memory, thereby minimizing data movement and enhancing energy efficiency. While prior work has focused primarily on dense neural operations, depthwise convolution (DWC), a key operation in lightweight models like MobileNets, poses unique challenges due to its limited cross-channel data reuse and irregular access patterns. This work proposes a novel IMC architecture tailored for efficient DWC acceleration using memristors. Our design features a zig-zag selection-line topology that significantly improves memory utilization compared to conventional 1T1R crossbars while preserving dense operations' throughput and energy efficiency. We fabricate a system-on-chip (SoC) implementing the proposed architecture and experimentally validate its performance. Fabricated in a 65 nm complementary metal-oxide-semiconductor process, the SoC delivers a measured energy efficiency of 21.3 TOPS/W at 100 MHz and lifts the per-array weight utilization of depthwise layers to similar to 100%. End-to-end deployment of a tailored MobileNetV1 on the visual-wake-words dataset reaches an inference accuracy of 80.36%, on par with the same software model quantized to 4-bit precision. This first hardware demonstration of depthwise-separable convolution on a memristor-based IMC SoC establishes the readiness of memristor-based IMC for next-generation edge-artificial intelligence accelerators.
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