Due to a stray field formation from the alternating ferroelectric bound charges of the multidomain state of the ferroelectric thin films, the negative capacitance effect can emerge in the ferroelectric/dielectric bilayer devices. However, the capacitance behavior of the thin ferroelectric/dielectric stacked films in the nanoscale cylindrical structure deviated from the negative capacitance state to unpredicted other states. This work confirmed that the thin (2.0 - 3.0 nm) ferroelectric Hf0.33Zr0.67O2 layer could have a positive capacitance, infinite capacitance, or negative capacitance by controlling the thickness of the stacked dielectric Al2O3 layer thickness (1.0 - 3.0 nm). A detailed analytical model and numerical simulation based on phase-field modeling, considering the ferroelectric polarization bound charge compensation by the injected/trapped interfacial carriers and the geometry effect of the cylinder, precisely identified the change of the inhomogeneous stray field energy, which played a crucial role in determining the capacitance state. Further analysis of the models revealed that the capacitance variation is strongly correlated to the extent of the initial polarization charge compensation of the ferroelectric domains and leakage mechanisms. This work provides guidelines for developing the next-generation capacitors in dynamic random access memory.

In-memory computing (IMC) using memristor crossbar arrays offers a promising approach to accelerating neural networks by performing analog computation directly within memory, thereby minimizing data movement and enhancing energy efficiency. While prior work has focused primarily on dense neural operations, depthwise convolution (DWC), a key operation in lightweight models like MobileNets, poses unique challenges due to its limited cross-channel data reuse and irregular access patterns. This work proposes a novel IMC architecture tailored for efficient DWC acceleration using memristors. Our design features a zig-zag selection-line topology that significantly improves memory utilization compared to conventional 1T1R crossbars while preserving dense operations' throughput and energy efficiency. We fabricate a system-on-chip (SoC) implementing the proposed architecture and experimentally validate its performance. Fabricated in a 65 nm complementary metal-oxide-semiconductor process, the SoC delivers a measured energy efficiency of 21.3 TOPS/W at 100 MHz and lifts the per-array weight utilization of depthwise layers to similar to 100%. End-to-end deployment of a tailored MobileNetV1 on the visual-wake-words dataset reaches an inference accuracy of 80.36%, on par with the same software model quantized to 4-bit precision. This first hardware demonstration of depthwise-separable convolution on a memristor-based IMC SoC establishes the readiness of memristor-based IMC for next-generation edge-artificial intelligence accelerators.

This work presents a holistic co-optimization of 3D ferroelectric NAND (FeNAND) for energy-efficient and high-throughput analog computation-in-memory. The co-optimization covers cell properties, non-cell peripherals, and computational schemes. Our approach enhances multi-level capability through write algorithm tuning, reduces word-line transition power, and improves analog multiply-and-accumulate efficiency via in-page pipelining and splitting. As a result, computational throughput and energy efficiency of 3D FeNAND are improved by up to 16x and 4950x, respectively, compared to conventional 2D arrays.

Here, we demonstrate hybrid ferroelectric tunnel junctions (H-FTJs) that combine ferroelectric and resistive switching for analog computation in memory. The key of H-FTJs lies in the modulation of the effective tunneling thickness by the control of oxygen vacancy-based unconnected filaments in $\text{HfZrO}_{2}$. The H-FTJs exhibited high on-state conductance $\left(1.6 \times 10^{3}\right. \mathrm{S} / \text{cm}^{2}$) and on/off ratios $(32,000)$ compared to recent studies on $\text{HfZrO}_{2}$-based FTJs. We also fully integrated one-transistor-one-(H-FTJ) cross-bar arrays, and confirmed their analog multiply-accumulate operations (accuracy 91.9%) with high energy efficiency (224.4 TOPS/W) for inference tasks.

Analog Computing-In-Memory (ACiM) accelerators with multi-level cells (MLCs) offer high density and area benefits for DNNs. To enhance efficiency, ADC resolution needs to be minimized, but this introduces significant quantization errors, lowering accuracy. Additionally, device noise and ADC integral nonlinearity (INL) noise further degrade accuracy. To address these challenges, we propose a training method that reduces ADC resolution while compensating for noise generated in ACiM arrays. By incorporating pseudo-quantization noise into Partial-Sum Training (PST), our approach not only stabilizes PST but also trains the model to become robust to ACiM-specific noise effects. Experimental results based on an industry ReRAM technology show that our PST scheme demonstrates robust noise tolerance across various ACiM configurations and maintains accuracy degradation within 1% even in the presence of cell conductance variability and ADC INL noise, while enabling low-resolution ADCs that reduces area and energy consumption by up to 16x and 31x, respectively.

Analog compute-in-memory (ACiM) systems show promise for energy-efficient AI inference, but their performance is hindered by variations in conductance, resulting in reduced accuracy. This work investigates the impact of mean error, which represents the discrepancy between actual conductance values and their intended targets from the measured distribution of 256 kb analog resistive switching cells, on the accuracy of neural network models. We propose opposing mean error compensation (OMEC), a technique that mitigates these errors without necessitating alterations to the memory device. Through simulations, we illustrate that adjusting weight targets can lead to a remarkable improvement in the inference accuracy, elevating it from a mere 12.59% to an impressive 90.65%, without modifying the memory device.

With the advance of artificial intelligent (AI), analog computation-in-memory (A-CiM) has been extensively studied for edge-AI applications, due to their low power operations. In this study, we demonstrated the modulation of multi-level weight conductance of ferroelectric field-effect-transistor (FeFET) devices as a synaptic cell. For the precise conductance modulation of FeFET synapses, we developed the simulation framework by combining a ferroelectric switching model, FeFET threshold (Vth) model, and accurate MOSFET drain current model. Then, the poly-Si channel FeFET synapses confirmed the multi-level conductance states (≥ 16-level/cell) with ultra-low current levels and stable retention, which improves energy efficiency of inference for image classification.

In this study, understanding the switching mechanisms of selector only memory (SOM) led to implementation of TCAD, and advanced materials and processes were developed based on the optimized core circuit design and write-read scheme in the first fully integrated 16 nm half-pitch SOM for emerging Compute Express Link ™ (CXL) memory. We have achieved read window margin (RWM, 750 mV) including product-level raw bit error rate (RBER) and reliability such as drift-related persistency, read disturbance (RDT), high temperature data retention (> 10 years at 125°C) and cycle endurance (For median values, read> 10 9 , write> 10 8 , and write> 10 7 cycles for RBER 200 ppm).

Analog Computing-in-Memory is promising and energy-efficient AI acceleration hardware due to the elimination of von-Neumann bottleneck and adoption of resistive synaptic cell (RSC) as calculation element. However, the performance of ACiM declines due to the non-idealities of RSC. In this study, a novel noise-aware training method is introduced which is aware of real distribution of array-level RSC conductances to make large-scale ACiM with a robustness. By comparing the inference accuracies under different training methods and non-idealities, the gap between ideal software accuracy and simulated ACiM inference accuracy can be reduced to 3.85% when all non-idealities are optimized along with the introduction of the proposed noise-aware training method. The simulation results can provide a standard guide for understanding how each non-ideality contributes to inference accuracy and how the neural network should be trained to optimize with the ACiM.

Non-volatile memory-based analog computation-in-memory can improve energy efficiency and latency of artificial intelligence edge devices by minimizing the movement of data between processors and memories. Here, we developed reliable HfO 2 -based resistive synaptic cell (RSC) arrays with 16-level analog properties. We revealed that oxygen diffusion barriers not only suppress the negative-set phenomenon and but also improve retention properties. In addition, we fully integrated 256Kcell 1T1R cross-bar RSC arrays using a conventional CMOS process, and demonstrated their improved multiply–accumulate operations with ~94% accuracy.

For the first time, we demonstrated the ultra-high density 3D ferroelectric NAND (FeNAND) arrays for analog computation of hyperscale AI models. Interface trap density of gate stacks was controlled to induce multi-level weight conductance states (> 256 levels/cell) of 3D FeNAND cells. Then, we confirmed the high accuracy (87.8%) of analog multiply-accumulate operations in 3D FeNAND arrays. Our 3D FeNAND arrays improved A-CiM cell density by a factor of 4,000x than 2D arrays, thereby they can provide 1,000x higher compute efficiency (TOPS/mm2).

We demonstrate a high performance and cost effective cross point memory (CPM) technology for storage class memory(SCM) which consists of 20nm 1S1M (one selector one memory) unit cell for four-deck 256 Gb density. Novel process integration was developed to make a uniform Vt distribution for a sufficient read window margin (RWM) and a corresponding low raw bit error rate (RBER). However, in spite of the successful integration and excellent performances, it is expected that the scalability of the CPM will face the inevitable drawbacks such as severe thermal disturbance (TDB) and smaller write program margin which is due to the scaling limit of phase change memory component in CPM. Therefore SOM (selector only memory) is suggested as the alternative device for the next generation SCM.

We demonstrate a high-performance and cost-effective cross-point memory (CPM) technology for two-deck 128 Gb storage class memory (SCM). The unit MAT size is 16 Mb consisting of a 2z nm 1S1M (one selector one memory) structure that is patterned by only two ArF-i steps per deck for a low cost per bit. The formidable task of self-align etch is enabled by the use of state-of-the-art etching and integration technology, which otherwise easily leads to hard fail or poor cell characteristics and reliabilities. New phase change materials (N-PCMs) are developed to have a large V t window and a uniform V t distribution for a sufficient read window margin (RWM) and a corresponding low raw bit error rate (RBER). New chalcogenide selectors (NCSs) are also developed to provide low V t instability and very low leakage current. The new CPM is able to provide a sufficient RWM for 16 Mb MATs with very low latencies of write (set ≤ 300 ns) and read (≤ 100 ns). We also demonstrate its decent write disturbance and high reliabilities such as endurance and thermal retention.

In order to realize the high density array device and suppress the disturbance between the cells, ReRAM also seem to need a selective device same as a diode in PCRAM. Still, while appropriate bipolar selective device doesn't show up, the tunnel barrier oxide embedded in ReRAM stack is one of the promising candidates for selective device of bipolar resistive switching memory. Additionally, using a tunnel barrier has a benefit to reduce the switching current. In this paper, bipolar memory devices with oxides such as HfOx, ZrOx and AlOx as a tunnel barrier were fabricated with 40 ~ 80nm cell size. We showed that the switching current and inherent switching mechanism can be successfully controlled by proper tunnel barrier materials and stacks.

For the first time, very fast (10ns at even Reset) and high reliable (150°C 100h) ReRAM memory was demonstrated at 54 nm 256k bits array. Reset current successfully decreased up to 20uA using Al2O3 which acts as a tunnel barrier and filament source in TiO2/Al2O3 stack. From statistical analysis, the possibility of increasing array size and the key factor of resistance distribution were investigated.