A Novel Bus Arbiter Based on Group Decision Algorithm

The arbiter is an essential component of the system-on-chip (SoC), network-on-chip (NoC), and classic interconnect bus, which is located in the critical path of these systems. The multi-master interconnect system has various performance limitations, but an effective arbiter can handle the contention caused by more than one master requesting access at once, preventing system performance degradation. For the advanced microcontroller bus architecture (AMBA), particularly for the advanced high-performance bus (AHB) frequently utilized in SoC design, the group decision (GD) bus arbiter is proposed. To combine the benefits of various arbitration systems and create a new priority sequence, the Borda concept is introduced. In contrast to the fixed priority (FP) bus, the frequently requested response from the masters can be quickly satisfied in the GD bus. In a multi-master SoC, our method can reduce the waiting time of masters that frequently access the bus by 50% in comparison to the round-robin (RR) bus, thus preventing the hunger issues. Moreover, our system uses VCS and Verdi for co-simulation, and utilizes the Design Compiler for synthesis. The results of the experiment show that a GD arbiter of 16 masters can reduce the waiting time to a certain extent and achieve 12.5% of the bus occupancy rate of commonly used masters compared to the bus with FP or RR arbiter.