Magnetoelectric (ME) antennas driven by acoustic excitation achieve electromagnetic radiation with high energy conversion efficiency and compact dimensions down to the centimeter scale. This makes them highly promising for portable very low frequency (VLF) communication applications. However, inevitable fabrication tolerances and other variations among ME antenna elements lead to phase inconsistencies, resulting in destructive interference of the array quasi-static near field and severely limiting practical performance. To address this issue, this letter presents a closed-loop phase self-calibration system based on an FPGA. Operating at a center frequency of 13.6 kHz, the system performs phase detection and automatic compensation in a single closed loop at startup, ensuring all antenna elements are initially phase-aligned. Experimental results demonstrate that, of the four ME antenna elements, the initial phase difference between ME1 and ME4 is close to 180°. After calibration, the magnetic flux density at 1 m is 7.9 times that of the uncalibrated case, and the magnetic flux density of the uncalibrated four-element array is lower than that of a single antenna. This study provides an effective solution for controlling the phase consistency of magnetoelectric antenna arrays.

This work presents a valley-sensed emulated peak current-mode controlled buck converter specifically optimized for high-performance double data rate synchronous dynamic random access memory (DDR SDRAM) applications. In this work, a dual-channel synchronous buck converter is designed to provide a low voltage required for DDR applications. Building upon traditional emulated peak current-mode control, an innovative circuit structure with configurable pre-bias current sensing is introduced. This enhancement ensures that current sensing components are protected from high voltage stress and prevents sub-harmonic oscillations in the current sensing circuit. More importantly, it enables bidirectional switching of source and sink currents, which is essential for DDR power supply solutions. Experimental verification and testing results demonstrate that the dual-channel buck converter has an input voltage range of 3.3 V to 15 V, with a maximum output sourcing current of 6 A and a peak sinking current of 3 A. The chip is fabricated using 180 nm Bipolar-CMOS-DMOS (BCD) process technology, featuring a minimum turn-on time of 132 ns, a minimum turn-off time of 400 ns, and an operating frequency of 300 kHz. The overall chip dimensions are 2.2 mm x 3.1 mm, while the core area, excluding pads, measures 1.8 mm x 2.7 mm.

This paper designs a low temperature drift, low jitter on-chip oscillator applied to a 32-bit ultra-high precision, 38.4 kS/s sampling rate sigma-delta analog-to-digital converter (SD ADC). To enhance the flexibility of the design, three clock source mode configurations are provided to offer more functionality for the 32-bit ultra-precision SD ADC chip. Two chip pins are used to implement the mode switching, thereby reducing the number of pins required and improving system adaptability. Moreover, the on-chip clock needs to have extremely high quality to meet the requirements of the 32-bit ultra-high precision SD ADC. This paper effectively reduces clock jitter and temperature drift by employing a low temperature drift reference circuit and a calibrated switched capacitor circuit. Based on the TSMC 0.25 m CMOS process, the circuit is designed and simulated. Simulation results show that at the standard frequency of 7.3728 MHz, the maximum average clock jitter is 100 ps. The temperature drift in the range of − 55 to 125 ^∘ C is only Δ 1.2 MHz, and the total frequency variation under five process corners (CONER) is only Δ 0.303 MHz. The clock process and temperature frequency error are less than 10 W , with an operating current of only 113 A .

This brief proposes a bit-serial compute-transfer architecture tailored for high-speed data processing across chip-to-chip links. Our design merges computation and transmission at the physical layer via a voltage-mode logic (VML) interface, without intermediate packing or unpacking. In SMIC 0.13 mu m CMOS, the architecture achieves 1 Gbps per channel at 1 GHz, delivering 0.625 GOPS to resource-constrained edge devices. While overall energy efficiency is lower than that of computing-only designs, the proposed structure excels in area, gate density, and scalability. This compute-transfer architecture reduces bandwidth bottlenecks and deserialization overhead in multi-chip systems, offering a modular building block for future neural network accelerators.

With the growth of deep learning and machine learning applications, an efficient processing element array (PEA) has become increasingly important. To address this need, this paper introduces a quantized bit-serial PEA, which improves data reusability by integrating a weight ring (WR) dataflow mechanism and increases operation frequency through the use of bit-serial circuits. This design substantially reduces the number of feature map accesses, thereby optimizing data processing efficiency. A key aspect of our approach is the use of quantization techniques. By converting floating-point values to signed 8-bit fixed-point numbers, we reduce computational complexity and ease memory bandwidth pressure. We briefly discuss that ignoring bias terms may not impact model inference accuracy when the appropriate neural network type and dataset are chosen. Our proposed WR dataflow, inspired by the weight stationary (WS) dataflow, only updates the outdated row with a new row. This not only boosts data reuse rates but also diminishes costly data access operations. Notably, the 3 x 3 WR PEA requires 38.54% of the off-chip accesses per second as compared to the 3 x 3 WS PEA and merely 11.25% compared to its no local reuse (NLR) PEA counterpart. Empirical results show its excellent tradeoff between area, power, and speed, ensuring robust data reuse efficiency. By combining quantization and WR dataflow, our high-reuse, quantized bit-serial PEA offers a fresh perspective on deep learning hardware design.

Bit-serial neural network accelerators address the growing need for compact and energy-efficient deep learning tools. Traditional neural network accelerators, while effective, often grapple with issues of size, power consumption, and versatility in handling a variety of computational tasks. To counter these challenges, this paper introduces an approach that hinges on the integration of bit-serial processing with advanced dataflow techniques and architectural optimizations. Central to this approach is a column-buffering (CB) dataflow, which significantly reduces access and movement requirements for the input feature map (IFM), thereby enhancing efficiency. Moreover, a simplified quantization process effectively eliminates biases, streamlining the overall computation process. Furthermore, this paper presents a meticulously designed LeNet-5 accelerator leveraging a convolutional layer processing element array (CL PEA) architecture incorporating an improved bit-serial multiply–accumulate unit (MAC). Empirically, our work demonstrates superior performance in terms of frequency, chip area, and power consumption compared to current state-of-the-art ASIC designs. Specifically, our design utilizes fewer hardware resources to implement a complete accelerator, achieving a high performance of 7.87 GOPS on a Xilinx Kintex-7 FPGA with a brief processing time of 284.13 μs. The results affirm that our design is exceptionally suited for applications requiring compact, low-power, and real-time solutions.

We find that the previously reported P-edge N-Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET) and dummy gate-assisted (DGA) NMOSFET, to resist the total ionizing dose (TID) effect, have a fatal drawback in that they can only work under a very low drain voltage (Vdd). This paper proposes and demonstrates an improved structure, called P+ edge source NMOS (PES-NMOS), in which the heavily P+ doped belts are only formed on both sides of the source region close to the shallow trench isolation (STI). Both the TCAD software simulations and radiation experiments show that the turn-off current (Ioff) of the PES-NMOS device under 1.8 V Vdd is about 4 to 5 orders of magnitude smaller than that of the control group without reinforcement structure at 300 krad(Si) TID. This result proves that the PES-NMOS can well resist the TID effect and solve the fatal drawback of the reported structures. With the continuous progress of the CMOS process, the thickness of gate oxide becomes very thin, while STI is relatively thick, so the total dose effect on STI is still significant. Therefore, the importance of using the PES-NMOS to suppress the parasitic channel of STI and overcome the shortcomings of the ELT is increasing. Index terms: P+ edge source NMOS, total ionizing dose(TID) effect, radiation experiments, radiation hardening by design(RHBD).

Bit-serial multiply-accumulate units (MACs) play a crucial role in various hardware accelerator applications, including deep learning, image processing, and signal processing. Despite the advantages of bit-serial MACs, such as a small footprint, full hardware utilization, and high frequency, their serial nature can lead to high latency and potentially compromised performance. This study investigates the potential of bit-serial solutions by applying Booth encoding to bit-serial multipliers within MACs to enhance area and power efficiencies. We present two types of bit-serial MACs based on radix-2 and radix-4 Booth encoding multipliers, respectively. Their performance is assessed through simulations and synthesis results, demonstrating the benefits of the proposed approach. The radix-4 Booth bit-serial MAC improves power and area efficiencies compared to the original bit-serial MAC. Operating at TSMC 90 nm and 150 MHz, our design exhibits a remarkable 96.39% reduction in area-power-product (APP). Moreover, the prototype verification on a Xilinx Kintex-7 FPGA proved successful. The proposed solution offers significant advantages in energy efficiency, area reduction, and APP, making it a promising candidate for next-generation hardware accelerators in offline inference, low-power devices, and other applications.

The IC industry in the Chinese mainland has encountered the difficulty caused by the embargo on lithography machines in developing state-of-the-art semiconductor IC processes. For the first time, this work fabricates out the HVTFET which we have independent intellectual property rights. A 50 nm channel length N HVTFET device is fabricated successfully using a 0.35 µm process, and its characteristics are close to those of TSMC’s 55 nm planar N MOSFET. The experimental results of this paper have two important significances. First, it shows that the fabrication of the advanced ICs in the Chinese mainland can get rid of the limitation of the lithography machine by using the HVTFET. Second, it shows that it is possible to decrease the chip area by about 3/4 by using the HVTFET structure for the ICs with 28 nm and above planar MOS processes, which are quite common in China.

The arbiter is an essential component of the system-on-chip (SoC), network-on-chip (NoC), and classic interconnect bus, which is located in the critical path of these systems. The multi-master interconnect system has various performance limitations, but an effective arbiter can handle the contention caused by more than one master requesting access at once, preventing system performance degradation. For the advanced microcontroller bus architecture (AMBA), particularly for the advanced high-performance bus (AHB) frequently utilized in SoC design, the group decision (GD) bus arbiter is proposed. To combine the benefits of various arbitration systems and create a new priority sequence, the Borda concept is introduced. In contrast to the fixed priority (FP) bus, the frequently requested response from the masters can be quickly satisfied in the GD bus. In a multi-master SoC, our method can reduce the waiting time of masters that frequently access the bus by 50% in comparison to the round-robin (RR) bus, thus preventing the hunger issues. Moreover, our system uses VCS and Verdi for co-simulation, and utilizes the Design Compiler for synthesis. The results of the experiment show that a GD arbiter of 16 masters can reduce the waiting time to a certain extent and achieve 12.5% of the bus occupancy rate of commonly used masters compared to the bus with FP or RR arbiter.

In this paper, a Hetero-junction Vertical Trench MOSFET (HVTFET) is proposed. The HVTFET has a multilayer structure. Compared with FinFETs and GAAs, the HVTFET provides a new method to effectively overcome the DIBL effect of the small-size IC. The channel length L ch of HVTFET is determined by the thickness of the epitaxial channel region, so the L ch can be reduced greatly, therefore the operating frequency of the HVTFET can be greatly increased. The HVTFET can achieve higher V dd by increasing the length of the low-doped drain region or reducing its doping concentration. The 7nm HVTFET simulation model has been established by using Sentaurus TCAD and it can work normally. The HVTFET breaks though the traditional IC reduction rule, and the HVTFET will lead IC to move forward in the future.

[目的/意义]流动性是证券市场的生命力,理解流动性与资产定价之间的关系是理解金融危机的核心.2015年中国股灾的发生使得流动性成为关注焦点,更引发了对股灾过程中相关交易机制如何影响市场流动性的思考.[设计/方法]通过系统回顾证券市场流动性相关的研究文献,包括流动性的定义、流动性的测度、流动性与资产定价的关系,以及流动性共振及其影响因素,对2015年股灾发生的微观机理以及杠杆交易和涨跌幅限制在股灾过程中的作用机制进行了重点剖析和评述.[结论/发现]杠杆交易的强制平仓机制使得股市在下行过程中形成了严重的"流动性螺旋"效应,而价格涨跌幅限制进一步加剧了市场的流动性枯竭,最终导致股灾发生.

分别采用EKOP模型、VPIN模型和VWPIN模型测度了中国证券市场个股的知情交易概率,并实证检验了知情交易概率因子在资产定价中的作用.研究结果表明,基于物理时间和交易量加权的VWPIN模型结合了经典EKOP模型和VPIN模型的优点,可以更简单地估计个股日内任意时间窗口下的信息不对称程度.进一步,关于资产定价的检验结果表明,在控制相关影响因素之后,采用VWPIN模型估计得到的知情交易概率因子与个股收益率之间呈现显著的正相关性,符合理论预期.

P2P借贷让借款人可以通过借款陈述文本去获得投资者的信任,所以借款陈述又成为投资者识别借款人违约风险的重要信息来源.但是如何解读复杂的、不规则的、包含各种信息的借款陈述面临较大挑战.针对违约风险的两个来源:还款能力和还款意愿,以及它们的潜在因素,从P2P借贷平台‘人人贷’借款项目中的借款陈述文本中,通过人工识别提取了文字特征信息、反映还款能力和还款意愿的信息以及对资金需求的情感特征信息,并检验这些信息对识别借款人违约风险的显著性.研究发现借款陈述文本的字数越多、存在重复语句,违约风险越大;借款陈述文本中存在还款能力信息,或者同时存在表示还款意愿的保证性语言以及对自己信用状态补充说明的信息,则违约风险越小;借款人在情感上表现出对资金需求的急切性越高,违约风险越大.研究结论为将来运用程序实现智能文本算法识别借款陈述文本中的违约信息提供了研究方向.

An idea of applying a film of high-k (HK) material to the trench lateral double-diffused MOSFET (LDMOS) is proposed and studied by simulation. Through introducing an HK film around the SiO2 trench, the flow of electric flux is guided, and the distribution of the surface electric field is modulated. As a result, the tradeoff relationship between breakdown voltage (BV) and specific ON-resistance (R-ON,R- sp) is improved. Simulation results indicate that the HK film with a permittivity of 475 and a thickness of 400 nm can effectively reduceRON, sp at the BV class of 200 V. Compared with the conventional device without HK, the proposed one is in a position to save about 60% of the chip area, while they are having the approximateperformance andmanufacturing complexity. Hence, the application of HK film is promising to improve the cost performance of trench LDMOS.

个股与市场总体之间的流动性协动在证券市场中普遍存在.选取沪深两市A股上市公司股票为研究样本,利用2015年股灾期间的日交易数据,实证分析杠杆交易是否是股灾中个股产生流动性协动的驱动因素,以及个股的流动性协动是否对其股价跌幅存在显著影响.实证结果发现,股灾中个股的流动性受到高杠杆股票组合流动性变动的显著影响,且杠杆交易越多的个股受到的影响越大,表明杠杆交易是股灾中个股流动性协动的重要驱动因素.进一步的研究表明,杠杆交易越多,个股股灾中的价格跌幅越大,并且个股的流动性协动程度对股价跌幅具有显著的正向影响.

The state-of-art Si Matel-Oxide-Semiconductor Field-Effect-Transistor (MOS-FET) meets the problem of the Power Consumption (PC) can not be effecively deceased guided by the Moore’s Law as before. The GFET has the problem of the device can not be effectively turned off, since the band-gap of the graphene is zero. To solve these problems, noticing the amount of the carriers in the 2 dementional semiconductor material is limited, we propose a Matel-Semi-Insulator-Semiconductor Field-Effect-Transistor (MSIS-FET) to replace the traditional MOS-FET. We verify our idea by fabricating the graphene MSIS-FETs using the natural Aluminium-oxide (Al-oxide) as the semi-insulator gate dielectric. From MSIS-FETs fabricated, we obtain following experimental results. The graphene MSIS-FET is turned off very well, a recorded high Ids on/off ratio of 5 × 107 is achieved. A saddle and close-loop shape transfer feature of Ids-Vgs is obtained first time for transistors. A non-volatile memory characteristics is observed. A carrier re-injection principle and a super-Low PC mechanism for semiconductor devices and integrated circuits (ICs) are found from the transfer feature of the graphene MSIS-FET. It is shown that the PC of the semiconductor devices and (ICs) can be reduced by over three orders of magnitude by using this new mechanism.

A design concept of variation vertical doping is proposed to upgrade the deep-trench lateral double-diffused metal–oxide–semiconductor field-effect transistor. Due to the proposal, a drift region in the form of charge-balance super-junction is first gained in such a device. Hence, the relationship between the breakdown voltage and the specific on-resistance is significantly improved. Numerical simulations demonstrate that the proposal is valid to increase the theoretical limit of the figure of merit to be about 44.9 MW/cm $^{\textsf {2}}$ , more than twice of that of the prior art. Besides, a feasible realization method is presented and studied.

改革开放40年,中国经济高速增长,关键原因在于交易成本的降低和交易效率的提高.随着互联网、大数据、人工智能等具有"电子信息+"特色的新兴技术的出现,交易成本将进一步降低,新技术、新产品、新产业、新业态、新模式将不断涌现,各种新经济形态会加速发展.

对混成系统进行安全性验证是计算机领域具有重要意义和挑战性的课题,传统的测试仿真技术不足以确保系统的绝对安全性和完备性.基于形式化方法是根据混成系统的形式规范与属性,使用数学方法证明其正确性或非正确性.对温控系统实现了抽象算法的形式化,首先对线性混成系统的状态空间进行分割,然后将其转化为图的可达性问题,利用图算法求解,最终对系统进行了安全性验证.实验结果表明,采用形式化方法对混成系统进行安全性验证具有较高的可靠性与可信性.